Visible to Intel only — GUID: mwh1410383726085
Ixiasoft
Visible to Intel only — GUID: mwh1410383726085
Ixiasoft
2.4.1.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive)
If you define multiple clocks for the same node, you can use clock group assignments with the logically_exclusive option to declare clocks as mutually exclusive. This technique can be useful for multiplexed clocks.
For example, consider an input port that is clocked by either a 100-MHz or 125-MHz clock. You can use the logically_exclusive option to declare that the clocks are mutually exclusive and eliminate clock transfers between the 100-MHz and 125-MHz clocks, as the following diagrams and example SDC constraints show:
Example SDC Constraints for Internal Clock Mux
# Create a clock on each port create_clock -name clk_100 -period 10 [get_ports clkA] create_clock -name clk_125 -period 8 [get_ports clkB] # Create derived clocks on the output of the mux create_generated_clock -name mux_100 -source [get_ports clkA] \ [get_pins clkmux|combout] create_generated_clock -name mux_125 -source [get_ports clkB] \ [get_pins clkmux|combout] -add # Set the two clocks as exclusive clocks set_clock_groups -logically_exclusive -group {mux_100} -group {mux_125}
Example SDC Constraints for External Clock Mux
# Create virtual clocks for the external primary clocks create_clock -period 10 -name clkA create_clock -period 20 -name clkB # Create derived clocks on the port clk create_generated_clock -name mux_100 -master_clock clkA [get_ports clk] create_generated_clock -name mux_125 -master_clock clkB [get_ports clk] -add # Assume no clock network latency between the external clock sources & the \ clock mux output set_clock_latency -source 0 [get_clocks {mux_100 mux_125}] # Set the two clocks as exclusive clocks set_clock_groups -physically_exclusive -group mux_100 -group mux_125