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1.1. Compilation Overview
1.2. Using the Node Finder
1.3. Design Analysis & Elaboration
1.4. Design Synthesis
1.5. Design Place and Route
1.6. Incremental Optimization Flow
1.7. Fast Forward Compilation Flow
1.8. Full Compilation Flow
1.9. HSSI Dual Simplex IP Generation Flow
1.10. Exporting Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Synthesis Language Support
1.15. Synthesis Settings Reference
1.16. Fitter Settings Reference
1.17. Design Compilation Revision History
1.4.3.1. Registering the SDC-on-RTL SDC File
1.4.3.2. Applying the SDC-on-RTL Constraints
1.4.3.3. Inspecting SDC-on-RTL Constraints
1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files
1.4.3.5. Using Entity-Based SDC-on-RTL Constraints
1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software
1.4.3.7. Example: Using SDC-on-RTL Features
1.10.1. Exporting a Version-Compatible Compilation Database
1.10.2. Importing a Version-Compatible Compilation Database
1.10.3. Creating a Design Partition
1.10.4. Exporting a Design Partition
1.10.5. Reusing a Design Partition
1.10.6. Viewing Quartus Database File Information
1.10.7. Clearing Compilation Results
1.12.1. Compiler Optimization Modes
1.12.2. Precompiled Component (PCC) Generation Stage
1.12.3. Compilation on a Compute Farm
1.12.4. Allow Register Retiming
1.12.5. Automatic Gated Clock Conversion
1.12.6. Enable Intermediate Fitter Snapshots
1.12.7. Fast Preserve Option
1.12.8. Fractal Synthesis Optimization
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
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1.14.1. Verilog and SystemVerilog Synthesis Support
Quartus® Prime synthesis supports the following Verilog HDL language standards:
- Verilog-1995 (IEEE Standard 1364-1995)
- Verilog-2001 (IEEE Standard 1364-2001)
- SystemVerilog-2005 (IEEE Standard 1800-2005)
- SystemVerilog-2009 (IEEE Standard 1800-2009)
- SystemVerilog-2012 (IEEE Standard 1800-2012)
The following important guidelines apply to Quartus® Prime synthesis of Verilog HDL and SystemVerilog:
- The Compiler uses the Verilog-2001 standard by default for files with an extension of .v, and the SystemVerilog standard for files with the extension of .sv.
- If you use scripts to add design files, you can use the -HDL_VERSION command to specify the HDL version for each design file.
- Compiler support for Verilog HDL is case sensitive in accordance with the Verilog HDL standard.
- The Compiler supports the compiler directive `define, in accordance with the Verilog HDL standard.
- The Compiler supports the include compiler directive to include files with absolute paths (with either “/” or “\” as the separator), or relative paths.
- When searching for a relative path, the Compiler initially searches the current files’ directory location. If the Compiler cannot find the file, the Compiler next searches relative to all user libraries. Finally, the Compiler searches relative to the project directory.
- Quartus® Prime Pro Edition synthesis searches for all modules or entities earlier in the synthesis process than other Quartus software tools. This earlier search produces earlier syntax errors for undefined entities than other Quartus software tools.