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1.1. Compilation Overview
1.2. Using the Node Finder
1.3. Design Analysis & Elaboration
1.4. Design Synthesis
1.5. Design Place and Route
1.6. Incremental Optimization Flow
1.7. Fast Forward Compilation Flow
1.8. Full Compilation Flow
1.9. HSSI Dual Simplex IP Generation Flow
1.10. Exporting Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Synthesis Language Support
1.15. Synthesis Settings Reference
1.16. Fitter Settings Reference
1.17. Design Compilation Revision History
1.4.3.1. Registering the SDC-on-RTL SDC File
1.4.3.2. Applying the SDC-on-RTL Constraints
1.4.3.3. Inspecting SDC-on-RTL Constraints
1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files
1.4.3.5. Using Entity-Based SDC-on-RTL Constraints
1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software
1.4.3.7. Example: Using SDC-on-RTL Features
1.10.1. Exporting a Version-Compatible Compilation Database
1.10.2. Importing a Version-Compatible Compilation Database
1.10.3. Creating a Design Partition
1.10.4. Exporting a Design Partition
1.10.5. Reusing a Design Partition
1.10.6. Viewing Quartus Database File Information
1.10.7. Clearing Compilation Results
1.12.1. Compiler Optimization Modes
1.12.2. Precompiled Component (PCC) Generation Stage
1.12.3. Compilation on a Compute Farm
1.12.4. Allow Register Retiming
1.12.5. Automatic Gated Clock Conversion
1.12.6. Enable Intermediate Fitter Snapshots
1.12.7. Fast Preserve Option
1.12.8. Fractal Synthesis Optimization
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
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1.6.2.1. Running Snapshot Viewer
You can run the Snapshot Viewer to assist with timing closure and design analysis after running the Plan, Place, Route, or Finalize stages of the Fitter. The Snapshot Viewer allows you to run various analysis tasks from the Flow Navigator to achieve faster timing closure and maximize design performance.
Figure 81. Snapshot Viewer Flow Navigator
Design Task | Available at Snapshot | Snapshot Viewer Commands |
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Timing Closure—Analyze Failing Paths | Planned, Placed, Routed, Finalized |
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Placed, Routed, Finalized |
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Timing Closure—Analyze Clocking This task is available only for Stratix® 10 devices. |
Placed, Finalized | Show Global Clock Visualization—loads the Global Signal Visualization report for the snapshot that allows you to visualize clock sector utilization. |
Timing Closure—Analyze High Fanout Nets | Placed, Routed, Finalized |
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Timing Closure—Validate Constraints | Planned | Timing Exceptions—displays the Timing Exceptions Results report that identifies timing paths with hold or removal slack exceeding threshold. |
Planned, Placed, Finalized | Check Unregistered Ports—displays the Check Unregistered Ports Results report that identifies unregistered partition inputs and paths. | |
Timing Closure—Analyze Congestion | Placed, Routed, Finalized | Show Logic Lock Regions with Congestion Heat Map—the Chip Planner displays the Logic Lock regions in a congestion heat map for further analysis. |
The following sections describe each analysis task in detail.