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1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
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1.7.1. Setting Up the Development Kit
Follow these steps to set up the Intel® Stratix® 10 GX FPGA development kit before running the reference design.
- Set the Intel® Stratix® 10 GX FPGA development kit switches to default position.
- Connect the HiLo loopback card on the HiLo memory interface.
- Connect the Intel® FPGA Download Cable to the Intel® Stratix® 10 GX FPGA development kit and your host machine.
Figure 13. Intel® Stratix® 10 GX FPGA Development Kit Board
- Click Tools > Programmer to program the <project directory> /phyllite_top.sof file into the Intel® Stratix® 10 GX FPGA development kit.
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