AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Public
Document Table of Contents

1.3.1.4. Clocking Scheme

This design uses 133 MHz clock from the Si5338 programmable oscillator. The PHY Lite for Parallel Interfaces IP core clock transfers data between the FPGA core logic and the IP core. The interface frequency between two PHY Lite for Parallel Interfaces IP core instances is 532 MHz.

Figure 3. Clocking Scheme for the PHY Lite for Parallel Interfaces Reference Design