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1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
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1.3.1.4. Clocking Scheme
This design uses 133 MHz clock from the Si5338 programmable oscillator. The PHY Lite for Parallel Interfaces IP core clock transfers data between the FPGA core logic and the IP core. The interface frequency between two PHY Lite for Parallel Interfaces IP core instances is 532 MHz.
Figure 3. Clocking Scheme for the PHY Lite for Parallel Interfaces Reference Design