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1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
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1.5.1. Per-Bit Deskew Concept
In real-life cases, the time DQ signal reaches the receiving side varies, depending on board skew, trace length mismatch, unit variation, and so on. All these factors may result a narrower DQ window than expected, as shown in the following figure:
Figure 5. Passing Window Result Before Per-Bit DeskewThis figure shows data are skewed due to board trace different and other factors, resulting a smaller passing window.
To overcome this, the PHY Lite for Parallel Interfaces IP core has the capability to calibrate each DQ/DQS pin separately. Successful per-bit calibration may improve the total DQS opening window. An example of the per-bit calibration (happening on the RX side) is shown in the following figures:
Figure 6. First DQ_0 Calibrated
Figure 7. Second DQ_1 Calibrated
Figure 8. Comparison of Passing Window Result Before and After Per-Bit Deskew