AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Public
Document Table of Contents

1.1. Features

  • A Nios® II processor to perform dynamic calibration for the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core.
  • A set of application program interface (API) to configure delay chains for the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core.