AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

Download PDF
ID 683220
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

1.3.1.3. DYN_CFG Controller

The DYN_CFG controller module consists of a Nios® II processor that acts as a centralized controller that handles the configuration of the PHY Lite for Parallel Interfaces IP core via Avalon® interface and handles control signals through parallel I/O modules.

The DYN_CFG controller module performs address translation to retrieve the physical address of the strobe or data pin to be configured. This module has forward and reverse paths. In the forward path, this module transmits data to the DUT_OUTPUT module. In the reverse path, this module receives data from the DUT_INPUT module.

Dynamic reconfiguration code is written in the Nios® II Software Build Tools for Eclipse and loaded into the instruction memory of the soft Nios® II processor. The Nios® II processor executes this code to perform calibrations. During processing, the Nios® II processor writes to the register in the I/O subsystem manager (I/O SSM) to change the DQS/DQ delay. Once the calibration is done and the data valid window is found, the Nios® II processor sets cfg_done to 1 and the interface to the IP core switches to the traffic generator. The traffic generator begins generating random data pattern and checks against the loopback data that comes back from the IP core input.

Level Two Title