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1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
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1.3.1.1. DUT_MODULE
This module consists of DUT_OUTPUT and DUT_INPUT instances with dynamic reconfiguration enabled.
The DUT_OUTPUT instance acts as transmitter, which transfers data from DYN_CFG controller or the traffic generator module. During configuration mode, the DYN_CFG controller sends the test data to the DUT_OUTPUT instance. In normal operating mode, the DUT_OUTPUT instance takes data from the traffic generator and sends to DUT_INPUT instance. In contrast, the DUT_INPUT instance acts as receiver. The data transmitted by the DUT_OUTPUT instance is looped back to the DUT_INPUT instance.