ID
683220
Date
9/11/2020
Public
Visible to Intel only — GUID: sum1554087119514
Ixiasoft
1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
Visible to Intel only — GUID: sum1554087119514
Ixiasoft
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
The PHY Lite for Parallel Interfaces reference design demonstrates the usage of the dynamic reconfiguration feature using the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core.
Two instances of PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopback using a custom HiLo loopback card on the Intel® Stratix® 10 GX FPGA development kit. One PHY Lite instance is configured as a transmitter (DUT_OUTPUT) and the other PHY Lite instance is configured as a receiver (DUT_INPUT).
Figure 1. Block Diagram—PHY Lite for Parallel Interfaces Reference Design System for Intel® Stratix® 10 Devices
Note: For the HiLo loopback card pin connections, refer to Appendix A: HiLo Loopback Card Pin Connections. For more information about the HiLo loopback card, contact Intel® Support.
Section Content
Features
Hardware and Software Requirements
Design System Architecture Overview
Dynamic Reconfiguration Overview
PHY Lite Per-Bit Overview
Compiling the Reference Design
Hardware Testing
Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Stratix 10 Devices
Appendix A: HiLo Loopback Card Pin Connections
Appendix B: Retrieving Lane and Pin Information
Appendix C: Decoding Parameter Table
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