AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

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ID 683220
Date 9/11/2020
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Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

1.6. Compiling the Reference Design

Follow these steps to set up and run the simulation reference design.

  1. Download the reference design files from Design Store and restore the design using Intel® Quartus® Prime Pro Edition software. For more information about the guideline to download and install the reference design files, refer to Getting Started with the Design Store in the related information.
  2. Open the reference design file (phylite_top.qpf) after successfully installing the design templates.
  3. From the Intel® Quartus® Prime Pro Edition software, open the dut_INPUT.qsys and dut_OUTPUT.qsys files. Make sure that the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP has the same configuration, as shown in the following figures:
    Figure 9. General Tab Configuration for DUT_INPUT Module
    Figure 10. Group 0 Tab Configuration for DUT_INPUT Module
    Note: Intel® recommends that you optimize the terminations (OCT) to achieve good signal integrity to help maximize the data margins obtained after calibration.
    Figure 11. General Tab Configuration for DUT_OUTPUT Module
    Figure 12. Group 0 Tab Configuration for DUT_OUTPUT Module
    Note: Intel® recommends that you optimize the terminations (OCT) to achieve good signal integrity to help maximize the data margins obtained after calibration.
  4. From the Intel® Quartus® Prime Pro Edition software, click Processing > Start Compilation to compile the reference design.
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