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1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
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1.3. Design System Architecture Overview
This reference design consists of a calibration engine (phylite_nios.qsys) and PHY Lite for Parallel Interfaces IP core instances (dut_INPUT.qsys and dut_OUTPUT.qsys) for data loopback and other functional blocks.
You can use this reference design as a starting point design and modify as required to suit your design application.
Figure 2. Block Diagram—PHY Lite for Parallel Interfaces Design System Architecture
The reference design consists of:
- DUT_MODULE:
- DUT_INPUT
- DUT_OUTPUT
- Traffic generator/checker module
- DYN_CFG Controller
- Clocking Scheme
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