ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide

Document Version Intel® Quartus® Prime Version Changes
2019.07.02 18.0
  • Updated the description of the read device dummy clock parameter in the Parameter Settings table.
  • Updated the description of the read_dummyclk port in the Input Ports table.
2018.05.15 18.0
  • Renamed Altera ASMI Parallel IP core to ASMI Parallel Intel® FPGA IP core per Intel rebranding.
  • Added support for EPCQ-A devices.
  • Updated the ASMI Parallel Intel® FPGA IP Core section to include guidelines on setting the MSEL pins for FPGA devices when using the AS x1 and AS x4 configuration schemes.
  • Updated the caution note in the ASMI Parallel Intel® FPGA IP Core section by providing guidelines to avoid corrupting the configuration bits in the configuration memory.
  • Added supported EPCQ-A devices in the Parameter Settings table.
  • Updated the description in the Choose I/O mode parameter in the Parameter Settings table.
  • Added reference to the Generic Serial Flash Interface Intel® FPGA IP Core User Guide for third-party flash devices.
  • Editorial edits.
Date Version Changes
May 2017 2017.05.31 Added support for Cyclone 10 LP and Cyclone 10 GX devices.
May 2016 2016.05.02
  • Added information about clkin maximum frequency should not exceed 20MHz or 25MHz.
  • Added note to state that the read_dummyclk must be enabled when fast read option is used.
  • Added information about allowing two clock cycles before sending a new signal after busy signal deasserted.
  • Added note about .rpd files read and write sequence starts with the LSB.
December 2014 2014.12.15
  • Added EPCQ-L devices.
  • Added sce[] port and definition.
  • Added die_erase parameter.
  • Updated diagrams to reflect newly added port and parameter.
July 2014 2014.07.18
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Renamed ALTASMI_PARALLEL megafunction to Altera ASMI Parallel IP core.
December 2013 4.2 Updated the following sections to include ex4b_addr information:
  • “Parameter Settings” on page 2–2.
  • “Input Ports” on page 2–8.
  • “ALTASMI_PARALLEL Block Diagram” on page 2–1.
  • Added “4-byte Addressing Exit Operation for an EPCQ256 Device” on page 3–17.
May 2013 4.1
  • Replaced the term dummy bytes with dummy cycles.
  • Removed the Use ‘die_erase’ port parameter in Table 2–1 on page 2–2. This parameter is only available for selected customers.
  • Updated the Use ‘read_address’ port parameter in Table 2–1 on page 2–2 to clarify that the width of the addr and read_address signals is 24 bit for other devices.
  • Updated the caution statement in “About This Megafunction” on page 1–1.
December 2012 4.0
  • Updated “Device Family Support” on page 1–3.
  • Added “Enable 4-byte Addressing Operation for an EPCQ256 Device” on page 3–16, “EPCQ Devices Extended SPI Dual and Quad I/O Instruction” on page 3–9, and “EPCQ Devices Read Dummy Clock Instruction” on page 3–9.
  • Updated Figure 2–1 on page 2–1 to include new ports.
  • Updated the following sections to include EPCQ information:

    “Read Memory Capacity ID from the EPCS/EPCQ Device” on page 3–2.

    “Fast Read Data from the EPCS/EPCQ Device” on page 3–7

    “Read Data from the EPCS/EPCQ Device” on page 3–5

    “Write Data to the EPCS/EPCQ Device” on page 3–10

    “Erase Memory in a Specified Sector on the EPCS/EPCQ Device” on page 3–14

    “Erase Memory in Bulk on the EPCS/EPCQ Device” on page 3–15

    “Protect a Sector on the EPCS/EPCQ Device” on page 3–4

    “Read Status Register of the EPCS/EPCQ Device” on page 3–13

  • Updated Table 2–1 on page 2–3 to include new parameters.
  • Updated Table 2–2 on page 2–10 to include en4b_addr and asmi_dataout ports information.
  • Updated Table 2–3 on page 2–13 to include asmi_dclk, asmi_scein, asmi_sdoin and asmi_dataoe ports information.
  • Change document to new user guide template.
September 2009 3.0
  • Removed “Device Family Support”
  • Added new information in “Introduction” on page 1
  • Added “Parameter Settings” on page 17
  • Added link to Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Datasheet
  • Updated to include information about read_rdid signal
  • Updated Figure 2 on page 3 to include Arria II GX and Stratix IV
  • Added Figure 1 on page 2
  • Removed “How to Contact Altera” and “Typographic Conventions” sections.
October 2007 2.4
  • Updated for new MegaWizard™ Plug-In Manager pages
  • Updated to include information about new fast_read command
May 2007 2.3
  • Added ArriaTM GX to list of supported devices in “Device Family Support”
  • Added Figure 1–2
  • Updated Figures 1-2, 2-2, 2-3, 2-4, and 2-5
March 2007 2.2
  • Removed Table 1-1 and added a list of supported devices.
  • Updated for the Quartus II software version 7.0 by adding support for Cyclone®® III device.
December 2006 2.1 Updated device family support to include Stratix III.
June 2006 2.0
  • Updated all screen shots.
  • Added the section “How to Use the Megafunction” on page 2-15.
November 2005 1.0 Initial release.
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