The vendor of the memory device. Select the memory vendor according to the memory vendor you use. For memory vendors that are not listed in the setting, select JEDEC with the nearest memory parameters and edit the parameter values according to the values of the memory vendor that you use. However, if you select a configuration from the list of memory presets, the default memory vendor for that preset setting is automatically selected.

The format of the memory device.

This parameter is automatically set to Discrete Device.

The maximum frequency at which the memory device can run.

The total number of DQ pins of the memory device. Limited to 8 to 24 bits.

The number of DQ bits per DQS group.

The number of DQS groups is calculated automatically from the Total interface width and the DQ/DQS group size parameters.

The number of chip-selects the IP core uses for the current device configuration.

Specify the total number of chip-selects according to the number of memory device.

The width of the clock bus on the memory interface.

The width of the row address on the memory interface.

The width of the column address on the memory interface.

The width of the bank address bus on the memory interface.

Specifies whether the DM pins of the memory device are driven by the FPGA. You can turn off this option to avoid overusing FPGA device pins when using x4 mode memory devices.

When you are using x4 mode memory devices, turn off this option for DDR3 SDRAM.

You must turn on this option if you are using Avalon® byte enable.

Turn on differential DQS signaling to improve signal integrity and system performance.

This option is available for DDR2 SDRAM only.

Specifies accesses within a given burst in sequential or interleaved order.

Specify sequential ordering for use with the memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the PHY Settings tab.

Specifies whether the DLL in the memory device is off or on during precharge power-down.

The number of clock cycles between the read command and the availability of the first bit of output data at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table.

Set this parameter according to the target memory speed grade and memory clock frequency.

The output driver impedance setting at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

The posted CAS additive latency of the memory device.

Enable this feature to improve command and bus efficiency, and increase system bandwidth. For more information about optimizing the memory controller, refer to related information.

The on-die termination resistance at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

Disable or enable auto selfrefresh.

Specifies the selfrefresh temperature as Normal or Extended.

The number of clock cycles from the releasing of the internal write to the latching of the first data in, at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table and set according to the target memory speed grade and memory clock frequency.

The mode of the dynamic ODT feature of the memory device. This is used for multi-rank configurations. For more guidelines about DDR2 and DDR3 SDRAM board layout, refer to the related information.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

Specifies the burst length.

Specifies accesses within a given burst in sequential or interleaved order.

Specify sequential ordering for use with the memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the PHY Settings tab.

Determines whether the DLL in the memory device is in slow exit mode or in fast exit mode during precharge power down. For more information, refer to memory vendor data sheet.

Determines the number of clock cycles between the READ command and the availability of the first bit of output data at the memory device. For more information, refer to memory vendor data sheet speed bin table.

Set this parameter according to the target memory speed grade and memory clock frequency.

Determines the output driver impedance setting at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

Determines the posted CAS additive latency of the memory device.

Enable this feature to improve command and bus efficiency, and increase system bandwidth.

Determines the on-die termination resistance at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

Determines the selfrefresh temperature (SRT). Select 1x refresh rate for normal temperature (0-85C)or select 2x refresh rate for high temperature (>85C).

Specifies the burst length.

Specifies accesses within a given burst in sequential or interleaved order.

Specify sequential ordering for use with the memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the PHY Settings tab.

Determines the number of clock cycles between the READ command and the availability of the first bit of output data at the memory device.

Set this parameter according to the target memory interface frequency. Refer to memory data sheet and also target memory speed grade.

Determines the output driver impedance setting at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.