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1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface
2.2. Intel® MAX® 10 DQ/DQS Groups
2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width
2.4. Intel® MAX® 10 Memory Controller
2.5. Intel® MAX® 10 External Memory Read Datapath
2.6. Intel® MAX® 10 External Memory Write Datapath
2.7. Intel® MAX® 10 Address/Command Path
2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. Intel® MAX® 10 Low Power Feature
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations
3.2. LPDDR2 Design Considerations
3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
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2.2. Intel® MAX® 10 DQ/DQS Groups
Different Intel® MAX® 10 devices and packages support different numbers of DQ/DQS groups for external memory interfaces.
Device | Package | I/O Bank (Right Side) |
Number of DQ Groups |
---|---|---|---|
x8 | |||
10M16 |
F256, U324, and F484 |
B5 | 1 |
B6 | 1 | ||
10M25 |
F256 |
B5 | 1 |
B6 | 1 | ||
F484 |
B5 | 1 | |
B6 | 2 | ||
10M40 |
F256 |
B5 | 1 |
B6 | 1 | ||
F484 |
B5 | 1 | |
B6 | 2 | ||
F672 |
B5 | 2 | |
B6 | 2 | ||
10M50 |
F256 |
B5 | 1 |
B6 | 1 | ||
F484 |
B5 | 1 | |
B6 | 2 | ||
F672 |
B5 | 2 | |
B6 | 2 |
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