Visible to Intel only — GUID: sam1396243804698
Ixiasoft
1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface
2.2. Intel® MAX® 10 DQ/DQS Groups
2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width
2.4. Intel® MAX® 10 Memory Controller
2.5. Intel® MAX® 10 External Memory Read Datapath
2.6. Intel® MAX® 10 External Memory Write Datapath
2.7. Intel® MAX® 10 Address/Command Path
2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. Intel® MAX® 10 Low Power Feature
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations
3.2. LPDDR2 Design Considerations
3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
Visible to Intel only — GUID: sam1396243804698
Ixiasoft
2. Intel® MAX® 10 External Memory Interface Architecture and Features
The external memory interface architecture of Intel® MAX® 10 devices is a combination of soft and hard IPs.
Figure 1. High Level Overview of Intel® MAX® 10 External Memory Interface SystemThis figure shows a high level overview of the main building blocks of the external memory interface system in Intel® MAX® 10 devices.
- The full rate data capture and write registers use the DDIO registers inside the I/O elements.
- PHY logic is implemented as soft logic in the core fabric.
- The memory controller is the intermediary between the user logic and the rest of the external memory interface system. The memory controller IP is a soft memory controller that operates at half rate. You can also use your own soft memory controller or a soft memory controller IP from Intel's third-party FPGA partners.
- The physical layer (PHY) serves as the bridge between the memory controller and the external memory DRAM device.
Section Content
Intel MAX 10 I/O Banks for External Memory Interface
Intel MAX 10 DQ/DQS Groups
Intel MAX 10 External Memory Interfaces Maximum Width
Intel MAX 10 Memory Controller
Intel MAX 10 External Memory Read Datapath
Intel MAX 10 External Memory Write Datapath
Intel MAX 10 Address/Command Path
Intel MAX 10 PHY Clock (PHYCLK) Network
Phase Detector for VT Tracking
On-Chip Termination
Phase-Locked Loop
Intel MAX 10 Low Power Feature