Visible to Intel only — GUID: sam1409642919589
Ixiasoft
1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface
2.2. Intel® MAX® 10 DQ/DQS Groups
2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width
2.4. Intel® MAX® 10 Memory Controller
2.5. Intel® MAX® 10 External Memory Read Datapath
2.6. Intel® MAX® 10 External Memory Write Datapath
2.7. Intel® MAX® 10 Address/Command Path
2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. Intel® MAX® 10 Low Power Feature
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations
3.2. LPDDR2 Design Considerations
3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
Visible to Intel only — GUID: sam1409642919589
Ixiasoft
3.1.2. DDR2/DDR3 Recommended Termination Schemes for Intel® MAX® 10 Devices
If you are creating interfaces with multiple DDR2 or DDR3 components where the address, command, and memory clock pins are connected to more than one load, follow these steps:
- Simulate the system to get the new slew rate for the DQ/DQS, DM, address and command, and clock signals.
- Use the derated tIS and tIH specifications from the DDR2 or DDR3 datasheet based on the simulation results.
- If timing deration causes your interface to fail timing requirements, consider duplication of these signals to lower their loading, and hence improve timing.
Note: Class I and Class II termination schemes in the following tables refer to drive strength and not physical termination.
Signal Type | SSTL 18 I/O Standard | FPGA–End Discrete Termination | Memory–End Termination 1 | Memory I/O Standard |
---|---|---|---|---|
DQ/DQS | Class I Rs = 50 Ω | 50 Ω parallel to VTT discrete | ODT75 4 | HALF 5 |
DM | Class I Rs = 50 Ω | — | ODT754 | HALF5 |
Address and command | Class I with maximum drive strength | — | 56 Ω parallel to VTT discrete | — |
Clock | Differential Class I Rs = 50 Ω | — | — |
I/O Standard | RS OCT | On Board Termination | |
---|---|---|---|
FPGA–End | Memory-End | ||
SSTL 15 Class 1 | 50 Ω without calibration | 80 Ω resistor | 40 Ω resistor |
Memory Interface Standard | I/O Standard | RS OCT | RUP, RDN (Ω) |
---|---|---|---|
DDR3 | SSTL-15 | 25 | 25 |
34 | 34 | ||
40 | 40 | ||
50 | 50 | ||
DDR3L | SSTL-135 | 34 | 34 |
40 | 40 | ||
DDR2 | SSTL-18 | 25 | 25 |
50 | 50 |
Related Information
4 ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
5 HALF is reduced drive strength.
6 x1 is a single-device load.
7 x2 is a two-device load.