Visible to Intel only — GUID: sam1396342210583
Ixiasoft
1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface
2.2. Intel® MAX® 10 DQ/DQS Groups
2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width
2.4. Intel® MAX® 10 Memory Controller
2.5. Intel® MAX® 10 External Memory Read Datapath
2.6. Intel® MAX® 10 External Memory Write Datapath
2.7. Intel® MAX® 10 Address/Command Path
2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. Intel® MAX® 10 Low Power Feature
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations
3.2. LPDDR2 Design Considerations
3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
Visible to Intel only — GUID: sam1396342210583
Ixiasoft
2.10. On-Chip Termination
The Intel® MAX® 10 devices support calibrated on-chip series termination (RS OCT) on the right side I/O banks.
- To use the calibrated OCT, use the RUP and RDN pins for each RS OCT control block.
- You can use each OCT calibration block to calibrate one type of termination with the same VCCIO.
You must set the RUP and RDN resistor values according to the RS OCT value. For example, if the RS OCT value is 34 Ω, then the set both RUP and RDN value to 34 Ω.
Related Information