Visible to Intel only — GUID: sam1400064769174
Ixiasoft
1. Intel® MAX® 10 External Memory Interface Overview
2. Intel® MAX® 10 External Memory Interface Architecture and Features
3. Intel® MAX® 10 External Memory Interface Design Considerations
4. Intel® MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for Intel® MAX® 10 Devices
6. Intel® MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
2.1. Intel® MAX® 10 I/O Banks for External Memory Interface
2.2. Intel® MAX® 10 DQ/DQS Groups
2.3. Intel® MAX® 10 External Memory Interfaces Maximum Width
2.4. Intel® MAX® 10 Memory Controller
2.5. Intel® MAX® 10 External Memory Read Datapath
2.6. Intel® MAX® 10 External Memory Write Datapath
2.7. Intel® MAX® 10 Address/Command Path
2.8. Intel® MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. Intel® MAX® 10 Low Power Feature
3.1. Intel® MAX® 10 DDR2 and DDR3 Design Considerations
3.2. LPDDR2 Design Considerations
3.3. Guidelines: Intel® MAX® 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
3.4. Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
3.5. Guidelines: Reading the Intel® MAX® 10 Pin-Out Files
Visible to Intel only — GUID: sam1400064769174
Ixiasoft
7. Document Revision History for the Intel® MAX® 10 External Memory Interface User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2022.10.31 | 21.1 |
|
2021.11.01 | 21.1 | Removed –I6 speed grade from contact information in the Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices table. All OPNs for –I6 speed grade are available in the Intel® Quartus® Prime Standard Edition software version 21.1 onwards. |
2021.04.01 | 16.1 |
|
2020.10.15 | 16.1 |
|
Date | Version | Changes |
---|---|---|
February 2017 | 2017.02.21 |
|
October 2016 | 2016.10.28 |
|
May 2016 | 2016.05.02 |
|
November 2015 | 2015.11.02 |
|
May 2015 | 2015.05.11 | Added on board termination recommendation for DDR3 component. |
May 2015 | 2015.05.04 |
|
December 2014 | 2014.12.15 |
|
September 2014 | 2014.09.22 | Initial release. |