DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 2/01/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Intel® Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Intel® Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

2. DisplayPort Design Examples

The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.

The DisplayPort Intel® FPGA IP TX-only design example demonstrates the DisplayPort source transmitting a fixed video resolution.

The DisplayPort Intel® FPGA IP RX-only design example demonstrates the DisplayPort Sink receiving video frame from external sources.

Table 7.   DisplayPort Intel® FPGA IP Design Example for Intel® Arria® 10 Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST TX-only DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex -
DisplayPort SST RX-only DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex -
DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR
DisplayPort SST parallel loopback without PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR
DisplayPort MST parallel loopback with PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR
DisplayPort MST parallel loopback without PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR
Note: DisplayPort SST parallel loopback without PCR design example and support for HBR3 are available only in the Intel® Quartus® Prime Pro Edition software.

Section Content
Intel Arria 10 DisplayPort SST Parallel Loopback Design Features
Intel Arria 10 DisplayPort MST Parallel Loopback Design Features
Enabling Adaptive Sync Support
Intel Arria 10 DisplayPort SST TX-only or RX-only Design Features
Design Components
Clocking Scheme
Interface Signals and Parameters
Hardware Setup
Simulation Testbench
DisplayPort Transceiver Reconfiguration Flow
Transceiver Lane Configurations

Level Two Title