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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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3.4.5.1. LED Functions
The LEDs on the board indicates the demonstration status.
LED | Functions |
---|---|
user_led[0] |
RX PHY ready status.
|
user_led[1] |
RX DisplayPort IP video lock status
|
user_led[2] |
RX HDCP1x IP decryption status.
|
user_led[3] |
RX HDCP2x IP decryption status.
|
user_led[5:4] |
TX data rate.
|
user_led[6] |
TX HDCP1x IP encryption status.
|
user_led[7] |
TX HDCP2x IP encryption status.
|