DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 2/01/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Intel® Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Intel® Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

2.7. Interface Signals and Parameters

The tables list the signals and parameter for the DisplayPort Intel® FPGA IP design example.
Table 15.  Top-Level Signals
Signal Direction Width Description
On-board Oscillator Signal
refclk1_p

Input

 1

100 MHz clock source used as IOPLL reference clock and Avalon® memory-mapped management clock

User Push Buttons and LEDs
user_pb[0]

Input

 1

Push button to trigger MSA print out during debug

user_pb[2]

Input

 1

Push button to switch to the next video stream, for the MST parallel loopback with PCR design example.

cpu_resetn

Input

 1

Global reset
user_led_g

Output

 8

Green LED display

Note: Refer to Hardware Setup for the on-board user LED functions.
DisplayPort FMC Daughter Card Pins on FMC Port A
fmca_gbtclk_m2c_p

Input

1

135 MHz dedicated transceiver reference clock from FMC port A

fmca_dp_m2c_p

Input

 N
DisplayPort RX serial data
Note: N = RX maximum lane count
fmca_dp_c2m_p

Output

 N
DisplayPort TX serial data
Note: N = TX maximum lane count
fmca_la_tx_p_10

Input

 1
DisplayPort RX cable detect
  • 1 = Cable detected
  • 0 = Cable not detected
fmca_la_rx_n_8

Input

 1
DisplayPort RX power detect
  • 1 = Power not detected
  • 0 = Power detected
fmca_la_tx_n_9

Input

 1

DisplayPort RX Aux In
fmca_la_rx_n_6

Output

 1

DisplayPort RX Aux Out
fmca_la_tx_p_9

Output

 1

DisplayPort RX Aux OE
fmca_la_rx_p_6

Output

 1
DisplayPort RX HPD
  • 1 = HPD asserted
  • 0 = HPD deasserted
fmca_la_rx_n_9

Input

 1
DisplayPort TX HPD
  • 1 = HPD asserted
  • 0 = HPD deasserted
fmca_la_tx_p_12

Input

 1

DisplayPort TX Aux In
fmca_la_rx_p_10

Output

 1

DisplayPort TX Aux Out
fmca_la_rx_n_10

Output

 1

DisplayPort TX Aux OE
fmca_la_tx_n_12

Output

 1

TX CAD for Bitec FMC Rev. 8

fmca_la_tx_p_14

Output

 1

TX CAD for Bitec FMC Rev. 10 and 11
FMC On-board Retimer Reconfiguration Interface
fmca_la_tx_p_0

Inout

 1

Bitec FMC Rev. 10: PS8460_SDA

Bitec FMC Rev. 11: MCDP6000_SDA
fmca_la_tx_n_0

Inout

 1

Bitec FMC Rev. 10: PS8460_SCL

Bitec FMC Rev. 11: MCDP6000_SDL
fmca_la_rx_p_0

Output

 1

Bitec FMC Rev. 10: PS8460_EQ0

Bitec FMC Rev. 11: Unused
fmca_la_rx_n_0 Output 1

Bitec FMC Rev. 10: PS8460_EQ1

Bitec FMC Rev. 11: Unused
fmca_la_tx_p_1 Output 1

Bitec FMC Rev. 10: PS8460_PDN

Bitec FMC Rev. 11: Unused
fmca_la_tx_n_1 Output 1

Bitec FMC Rev. 10: PS8460_CFG0

Bitec FMC Rev. 11: Unused
fmca_la_tx_p_2 Output 1

Bitec FMC Rev. 10: PS8460_CFG1

Bitec FMC Rev. 11: Unused
fmca_la_tx_n_2 Output 1

Bitec FMC Rev. 10: PS8460_CFG2

Bitec FMC Rev. 11: Unused
Table 16.   DisplayPort Intel® FPGA IP Signals (Platform Designer System)
Signal Direction Width Description
Clock and Reset
clk_100_in_clk

Input

 1

100 MHz clock to CPU sub-system
cpu_reset_bridge_in_reset_n

Input

 1

Reset to CPU sub-system (active low)
DisplayPort RX Signals
dp_rx_reset_bridge_in_reset_n

Input

 1

Reset to RX sub-system (active low)
dp_rx_clk_16_in_clk

Input

 1

RX Auxiliary clock (16 MHz)
dp_rx_dp_sink_clk_cal

Input

 1

RX reconfiguration calibration clock
dp_rx_pio_0_in_port

Input

 1

Push button IO for debug purpose
dp_rx_dp_sink_rx_audio_valid

Output

 1
RX Audio Interface
Note: M = RX audio channel
dp_rx_dp_sink_rx_audio_mute

Output

 1
dp_rx_dp_sink_rx_audio_infoframe

Output

 40
dp_rx_dp_sink_rx_audio_lpcm_data

Output

 M*32
dp_rx_dp_sink_rx_aux_in

Input

 1

RX auxiliary interface
dp_rx_dp_sink_rx_aux_out

Output

 1
dp_rx_dp_sink_rx_aux_oe

Output

 1
dp_rx_dp_sink_rx_hpd

Output

 1

RX HPD
dp_rx_dp_sink_rx_cable_detect

Input

 1

RX cable detect (active high)
dp_rx_dp_sink_rx_pwr_detect

Input

 1

RX power detect (active high)
dp_rx_dp_sink_rx_msa

Output

 217

DisplayPort RX MSA
dp_rx_dp_sink_rx_lane_count

Output

 5

DisplayPort RX lane count
dp_rx_dp_sink_rx_link_rate

Output

 2

RX Link Rate 2-bit indicator, used in PCR

  • RBR: 2‘b00
  • HBR: 2‘b01
  • HBR2: 2‘b10
  • HBR3: 2'b11
dp_rx_dp_sink_rx_link_rate_8bits

Output

 8

RX Link Rate 8-bit indicator, used in transceiver reconfiguration management

  • RBR: 0x06
  • HBR: 0x0A
  • HBR2: 0x14
  • HBR3: 0x1E
dp_rx_dp_sink_rx_ss_valid

Output

 1

DisplayPort RX secondary stream interface
dp_rx_dp_sink_rx_ss_data

Output

 160
dp_rx_dp_sink_rx_ss_sop

Output

 1
dp_rx_dp_sink_rx_ss_eop

Output

 1
dp_rx_dp_sink_rx_ss_clk

Output

 1
dp_rx_dp_sink_rx_stream_valid

Output

 1
RX post scrambler stream data. For debug purpose.
Note: S = RX symbols per clock
dp_rx_dp_sink_rx_stream_clk

Output

 1
dp_rx_dp_sink_rx_stream_data

Output

 S*32
dp_rx_dp_sink_rx_stream_ctrl

Output

 S*4
dp_rx_dp_sink_rx_vid_clk

Input

 1
DisplayPort RX video stream interface.
Note: B = RX bits per color, P = RX pixels per clock
dp_rx_dp_sink_rx_vid_sol

Output

 1
dp_rx_dp_sink_rx_vid_eol

Output

 1
dp_rx_dp_sink_rx_vid_sof

Output

 1
dp_rx_dp_sink_rx_vid_eof

Output

 1
dp_rx_dp_sink_rx_vid_locked

Output

 1
dp_rx_dp_sink_rx_vid_interlace

Output

 1
dp_rx_dp_sink_rx_vid_field

Output

 1
dp_rx_dp_sink_rx_vid_overflow

Output

 1
dp_rx_dp_sink_rx_vid_data

Output

 B*P*3
dp_rx_dp_sink_rx_vid_valid

Output

 P
dp_rx_dp_sink_rx_parallel_data

Input

 N *S*10
DisplayPort parallel data from RX Native PHY
Note: N = RX maximum lane count, S = RX symbols per clock
dp_rx_dp_sink_rx_std_clkout

Input

 N
CDR clock out from RX Native PHY
Note: N = RX maximum lane count
dp_rx_dp_sink_rx_restart

Output

 1

Reset signal to RX Native PHY Reset controller when RX data loses alignment. Triggered by the DisplayPort RX core.
dp_rx_dp_sink_rx_reconfig_req

Output

 1
Transceiver reconfiguration interface to the RX reconfiguration management module
Note: N = RX maximum lane count
dp_rx_dp_sink_rx_reconfig_ack

Input

 1
dp_rx_dp_sink_rx_reconfig_busy

Input

 1
dp_rx_dp_sink_rx_bitslip

Output

 N
dp_rx_dp_sink_rx_cal_busy input N
dp_rx_dp_sink_rx_analogreset

Output

 N
dp_rx_dp_sink_rx_digitalreset

Output

 N
dp_rx_dp_sink_rx_is_lockedtoref

Input

 N
dp_rx_dp_sink_rx_is_lockedtodata

Input

 N
dp_rx_dp_sink_rx_set_locktoref

Output

 N
dp_rx_dp_sink_rx_set_locktodata

Output

 N
DisplayPort TX Signals
dp_tx_reset_bridge_in_reset_n

Input

1

Reset to TX sub-system

dp_tx_clk_16_in_clk

Input

 1

TX Auxiliary clock (16 MHz)
dp_tx_dp_source_clk_cal

Input

 1

TX reconfiguration calibration clock
dp_tx_dp_source_tx_audio_valid

Input

 1
TX audio channel interface
Note: M = TX audio channel
dp_tx_dp_source_tx_audio_mute

Input

 1
dp_tx_dp_source_tx_audio_lpcm_data

Input

 M*32
dp_tx_dp_source_tx_audio_clk

Input

 1
dp_tx_dp_source_tx_aux_in

Input

 1

TX auxiliary interface
dp_tx_dp_source_tx_aux_out

Output

 1
dp_tx_dp_source_tx_aux_oe

Output

 1
dp_tx_dp_source_tx_hpd

Input

 1

TX HPD
dp_tx_dp_source_tx_link_rate

Output

 2

TX Link Rate 2-bit indicator, used in transceiver reconfiguration management

  • RBR: 2‘b00
  • HBR: 2‘b01
  • HBR2: 2‘b10
  • HBR3: 2'b11
dp_tx_dp_source_tx_link_rate_8bits

Output

 8

TX Link Rate 8-bit indicator, used in transceiver reconfiguration management

  • RBR: 0x06
  • HBR: 0x0A
  • HBR2: 0x14
  • HBR3: 0x1E
dp_tx_dp_source_tx_ss_ready

Output

 1

DisplayPort TX secondary stream interface
dp_tx_dp_source_tx_ss_valid

Input

 1
dp_tx_dp_source_tx_ss_data

Input

 128
dp_tx_dp_source_tx_ss_sop

Input

 1
dp_tx_dp_source_tx_ss_eop

Input

 1
dp_tx_dp_source_tx_ss_clk

Output

 1
dp_tx_dp_source_tx_vid_clk

Input

 1
DisplayPort TX video stream (VYSNC/HSYNC/DE) interface (only used when TX_SUPPORT_IM_ENABLE = 0)
Note: B = TX bits per color, P = TX pixels per clock.
dp_tx_dp_source_tx_vid_data

Input

 B*P*3
dp_tx_dp_source_tx_vid_v_sync

Input

 P
dp_tx_dp_source_tx_vid_h_sync

Input

 P
dp_tx_dp_source_tx_vid_de

Input

 P
dp_tx_dp_source_tx_im_clk

Input

 1
DisplayPort TX video image interface (only used when TX_SUPPORT_IM_ENABLE = 1)
Note: B = TX bits per color, P = TX pixels per clock.
dp_tx_dp_source_tx_im_sol

Input

 1
dp_tx_dp_source_tx_im_eol

Input

 1
dp_tx_dp_source_tx_im_sof

Input

 1
dp_tx_dp_source_tx_im_eof

Input

 1
dp_tx_dp_source_tx_im_data

Input

 B*P*3
dp_tx_dp_source_tx_im_valid

Input

 1
dp_tx_dp_source_tx_im_locked

Input

 1
dp_tx_dp_source_tx_im_interlace

Input

 1
dp_tx_dp_source_tx_im_field

Input

 1
dp_tx_dp_source_tx_parallel_data

Output

 N*S*10
DisplayPort parallel data to TX Native PHY
Note: N = TX maximum lane count, S = TX symbols per clock
dp_tx_dp_source_tx_std_clkout

Input

 N
TX Native PHY clock out
Note: N = TX maximum lane count
dp_tx_dp_source_tx_pll_locked

Input

 1

TX PLL locked indicator
dp_tx_dp_source_tx_reconfig_req

Output

 1
Transceiver Reconfiguration interface to TX reconfiguration management module
Note: N = TX maximum lane count
dp_tx_dp_source_tx_reconfig_ack

Input

 1
dp_tx_dp_source_tx_reconfig_busy

Input

 1
dp_tx_dp_source_tx_pll_powerdown

Output

 1
dp_tx_dp_source_tx_analog_reconfig_req

Output

 1
dp_tx_dp_source_tx_analog_reconfig_ack

Input

 1
dp_tx_dp_source_tx_analog_reconfig_busy

Input

 1
dp_tx_dp_source_tx_vod

Output

 N*2
dp_tx_dp_source_tx_emp

Output

 N*2
dp_tx_dp_source_tx_analogreset

Output

 N
dp_tx_dp_source_tx_digitalreset

Output

 N
dp_tx_dp_source_tx_cal_busy

Input

 N
Table 17.  RX PHY Top-Level Signals
Signal Direction Width Description
rx_cdr_refclk

Input

 1

RX Native PHY CDR reference clock. This design example uses 135 MHz.

dp_rx_clk_cal

Output

 1

50 MHz DisplayPort RX reconfiguration calibration clock. This clock must be synchronous to rcfg_mgmt_clk.

rx_cdr_resetn

Input

 1

RX Native PHY reset (active low)
video_pll_locked

Input

 1

This signal indicates that the video PLL (video clock and clk16) is stable and locked. Use as reset to the DisplayPort Intel® FPGA IP and the transceiver.

dp_rx_link_rate_8bits

Input

 8

RX link rate indicator, used in transceiver reconfiguration management

rx_rcfg_mgmt_reset

Input

 1

RX reconfiguration reset
rx_rcfg_mgmt_clk

Input

 1

RX reconfiguration management clock (100 MHz)

rx_rcfg_en

Output

 1

RX reconfiguration enable signal
rx_rcfg_write

Output

 1
Reconfiguration Avalon® memory-mapped interfaces that interact with Transceiver Arbiter
Note: N = RX maximum lane count (1, 2, or 4)
rx_rcfg_read

Output

 1
rx_rcfg_address

Output

 12
rx_rcfg_writedata

Output

 32
rx_rcfg_readdata

Input

 32
rx_rcfg_waitrequest

Input

 1
rx_rcfg_cal_busy

Input

 N
gxb_rx_rcfg_write

Input

 N
Reconfiguration Avalon® memory-mapped interfaces from Transceiver Arbiter
Note: N = RX maximum lane count (1, 2, or 4)
gxb_rx_rcfg_read

Input

 N
gxb_rx_rcfg_address

Input

 N*10
gxb_rx_rcfg_writedata

Input

 N*32
gxb_rx_rcfg_readdata

Output

 N*32
gxb_rx_rcfg_waitrequest

Output

 N
gxb_rx_rcfg_cal_busy

Output

 N
gxb_rx_clkout

Output

 N
RX Native PHY CDR clock out
Note: N = RX maximum lane count (1, 2, or 4)
gxb_rx_serial_data

Input

 N
DisplayPort Serial Data to RX Native PHY
Note: N = RX maximum lane count (1, 2, or 4)
dp_rx_parallel_data

Output

 N*S*10
DisplayPort parallel data to DisplayPort RX core
Note: N = RX maximum lane count (1, 2, or 4), S = RX symbols per clock (2 or 4)
dp_rx_restart

Input

 1

Reset signal to the RX Native PHY Reset controller when RX data loses alignment. Triggered by the DisplayPort RX core.

dp_rx_rcfg_req

Input

 1
Transceiver Reconfiguration interface from the DisplayPort RX core
Note: N = RX maximum lane count (1, 2, or 4)
dp_rx_rcfg_ack

Output

 1
dp_rx_rcfg_busy

Output

 1
dp_rx_is_lockedtoref

Output

 N
dp_rx_is_lockedtodata

Output

 N
dp_rx_bitslip

Input

 N
dp_rx_cal_busy

Output

 1
dp_rx_set_locktoref

Input

 N
dp_rx_set_locktodata

Input

 N
Table 18.  TX PHY Top-Level Signals
Signal Direction Width Description
tx_pll_refclk

Input

 1

TX transceiver PLL reference clock. This design example uses 135 MHz.

dp_tx_clk_cal

Output

 1

50 MHz DisplayPort TX reconfiguration calibration clock. This clock must be synchronous to rcfg_mgmt_clk.

tx_pll_resetn

Input

 1

TX transceiver PLL reset (active low)
video_pll_locked

Input

 1

This signal indicates that the video PLL (video clock and clk16) is stable and locked. Use as reset to the DisplayPort Intel® FPGA IP and the transceiver.

tx_cad

Output

 1

Driven to FMC card TX CAD. Tied to 0.
dp_tx_link_rate_8bits

Input

 8

TX Link Rate indicator, used in transceiver reconfiguration management.

  • RBR: 0x06
  • HBR: 0x0A
  • HBR2: 0x14
  • HBR3: 0x1E
tx_rcfg_mgmt_reset

Input

 1

TX reconfiguration reset
tx_rcfg_mgmt_clk

Input

 1

TX reconfiguration management clock (100 MHz)

tx_rcfg_en

Output

 1

TX reconfiguration enable signal
tx_rcfg_write

Output

 1
Reconfiguration Avalon® memory-mapped interfaces to Transceiver Arbiter
Note: N = TX maximum lane count (1, 2, or 4)
tx_rcfg_read

Output

 1
tx_rcfg_address

Output

 12
tx_rcfg_writedata

Output

 32
tx_rcfg_readdata

Input

 32
tx_rcfg_waitrequest

Input

 1
tx_rcfg_cal_busy

Input

 N
gxb_tx_rcfg_write

Input

 N
Reconfiguration Avalon® memory-mapped interfaces from Transceiver Arbiter
Note: N = TX maximum lane count (1, 2, or 4)
gxb_tx_rcfg_read

Input

 N
gxb_tx_rcfg_address

Input

 N*10
gxb_tx_rcfg_writedata

Input

 N*32
gxb_tx_rcfg_readdata

Output

 N*32
gxb_tx_rcfg_waitrequest

Output

 N
gxb_tx_rcfg_cal_busy

Output

 N
gxb_tx_clkout

Output

 N
Transceiver clock out
Note: N = TX maximum lane count (1, 2, or 4)
gxb_tx_serial_data

Output

 N
DisplayPort Serial Data from Transceiver
Note: N = TX maximum lane count
dp_tx_parallel_data

Input

 N*S*10
DisplayPort Parallel Data from DisplayPort TX Core
Note: N = TX maximum lane count (1, 2, or 4), S = TX symbols per clock (2 or 4)
dp_tx_rcfg_req

Input

 1
Transceiver Reconfiguration interface from DisplayPort TX Core
Note: N = TX maximum lane count (1, 2, or 4)
dp_tx_rcfg_ack

Output

 1
dp_tx_rcfg_vod

Input

 8
dp_tx_rcfg_emp

Input

 8
dp_txpll_rcfg_req

Input

 1
dp_txpll_rcfg_ack

Output

 1
dp_tx_rcfg_busy

Output

 1
dp_txpll_powerdown

Input

 1
dp_tx_cal_busy

Output

 N
dp_txpll_locked

Output

 1
Table 19.  Transceiver Arbiter Signals
Signal Direction Width Description
clk

Input

 1

Reconfiguration clock. This clock must share the same clock with the reconfiguration management blocks.

reset

Input

 1

Reset signal. This reset must share the same reset with the reconfiguration management blocks.

rx_rcfg_en

Input

 1

RX reconfiguration enable signal
tx_rcfg_en

Input

 1

TX reconfiguration enable signal
rx_rcfg_ch

Input

 2

Indicates which channel to be reconfigured on the RX core. This signal must always remain asserted.

tx_rcfg_ch

Input

 2

Indicates which channel to be reconfigured on the TX core. This signal must always remain asserted.

rx_reconfig_mgmt_write

Input

 1

Reconfiguration Avalon® memory-mapped interfaces from the RX reconfiguration management

rx_reconfig_mgmt_read

Input

 1
rx_reconfig_mgmt_address

Input

 10
rx_reconfig_mgmt_writedata

Input

 32
rx_reconfig_mgmt_readdata

Output

 32
rx_reconfig_mgmt_waitrequest

Output

 1
tx_reconfig_mgmt_write

Input

 1

Reconfiguration Avalon® memory-mapped interfaces from the TX reconfiguration management

tx_reconfig_mgmt_read

Input

 1
tx_reconfig_mgmt_address

Input

 10
tx_reconfig_mgmt_writedata

Input

 32
tx_reconfig_mgmt_readdata

Output

 32
tx_reconfig_mgmt_waitrequest

Output

 1
reconfig_write

Output

 1

Reconfiguration Avalon® memory-mapped interfaces to the transceiver

reconfig_read

Output

 1
reconfig_address

Output

 10
reconfig_writedata

Output

 32
rx_reconfig_readdata

Input

 32
rx_reconfig_waitrequest

Input

 1
tx_reconfig_readdata

Input

 1
tx_reconfig_waitrequest

Input

 1
rx_cal_busy

Input

 1

Calibration status signal from the RX transceiver

tx_cal_busy

Input

 1

Calibration status signal from the TX transceiver

rx_reconfig_cal_busy

Output

 1

Calibration status signal to the RX transceiver PHY reset control

tx_reconfig_cal_busy

Output

 1

Calibration status signal to the TX transceiver PHY reset control
Table 20.  Pixel Clock Recovery Signals

The PCR module in the dynamic generation design example is an enhanced version where 2 Fractional PLLs (FPLLs) are used.

Signal Direction Width Description
areset

Input

1

PCR reset
clk

Input

 1

Control loop clock (16 MHz)
clk_135

Input

 1

135 MHz clock
rx_link_clk

Input

1

RX Native PHY CDR clock out
rx_link_rate

Input

 2

RX link rate 2-bit indicator
rx_msa

Input

217

RX MSA
vidin_clk

Input

 1

RX video clock.

If MAX_LINK_RATE = HBR2 and PIXELS_PER_CLOCK = Dual, uses 300 MHz. Otherwise, fixed to 160 MHz.

vidin_data

Input

 B*P*3
RX video stream interface from RX core
Note: B = RX bits per color, P = RX pixels per clock.
vidin_valid

Input

 1
vidin_locked

Input

1
vidin_sof

Input

1
vidin_eof

Input

1
vidin_sol

Input

1
vidin_eol

Input

1
rec_clk

Output

 1

Reconstructed/recovered video clock
rec_clk_x2

Output

 1

Reconstructed/recovered video clock (2x faster); not used

vidout

Output

 B*P*3
TX video stream interface
Note: B = TX bits per color, P = TX pixels per clock.
hsync

Output

 1
vsync

Output

 1
de

Output

 1
field2

Output

 1
Table 21.  Pixel Clock Recovery ParametersYou can use these parameters to configure the clock recovery core.
Parameter Default Value Description
PIXELS_PER_CLOCK 1

Specifies how many pixels in parallel (for each clock cycle) are gathered from the DisplayPort RX core (1, 2 or 4).

BPP 24

Specifies the width (in bits) of a single pixel.

1 bit per pixel is equivalent to 3* bits per color.

CLK_PERIOD_NS 10

Specifies the period (in nanoseconds) of the clock signal connected to the port. In this design example, the value used is 62.

DEVICE_FAMILY Intel® Arria® 10

Identifies the family of the device used.

FIXED_NVID 0

Specifies the configuration of the DisplayPort RX received video clocking used.

  • 1 if GPU NVID is fixed to 'h8000
  • 0 if GPU NVID is not fixed

Select 0 if you require the PCR to inter-operate with any GPU.

Select 1 if you want to optimize resources but take note that this option may not work with certain GPUs.

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