Visible to Intel only — GUID: nfv1538446660158
Ixiasoft
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
Visible to Intel only — GUID: nfv1538446660158
Ixiasoft
2.11. Transceiver Lane Configurations
If you want to configure your design to use 1, 2 or 4 lanes targeting different versions of Bitec FMC daughter cards, you have to configure the pin assignments accordingly in the Intel® Quartus® Prime Pro Settings File (QSF).
To configure the DisplayPort Intel® FPGA IP design example using 1, 2 or 4 lanes, follow these steps:
- In both the DisplayPort Source and Sink parameter editors, set the Maximum lane count parameter to 1, 2 or 4.
- Generate the design example.
- Make the following assignments in the Assignment Editor.
Table 25. Pin Assignments for Bitec FMC Revision 8 or Earlier DisplayPort Pin Location ( Intel® Arria® 10 Development Kit)
Four Lanes Two Lanes One Lane Source BC7 fmca_dp_c2m_p[0] Not applicable Not applicable BC8 fmca_dp_c2m_n[0] BD5 fmca_dp_c2m_p[1] BD6 fmca_dp_c2m_n[1] BB5 fmca_dp_c2m_p[2] fmca_dp_c2m_p[0] BB6 fmca_dp_c2m_n[2] fmca_dp_c2m_n[0] BC3 fmca_dp_c2m_p[3] fmca_dp_c2m_p[1] fmca_dp_c2m_p[0] BC4 fmca_dp_c2m_n[3] fmca_dp_c2m_n[1] fmca_dp_c2m_n[0] Sink AW7 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] AW8 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] BA7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not applicable BA8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1] AY5 fmca_dp_m2c_p[2] Not applicable AY6 fmca_dp_m2c_n[2] AV5 fmca_dp_m2c_p[3] AV6 fmca_dp_m2c_n[3] Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable Table 26. Pin Assignments for Bitec FMC Revision 10 DisplayPort Pin Location ( Intel® Arria® 10 Development Kit) Four Lanes Two Lanes One lane Source BC7 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] BC8 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] BD5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not Applicable BD6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1] BB5 fmca_dp_c2m_p[2] Not Applicable BB6 fmca_dp_c2m_n[2] BC3 fmca_dp_c2m_p[3] BC4 fmca_dp_c2m_n[3] Sink AW7 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] AW8 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] BA7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not Applicable BA8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1] AY5 fmca_dp_m2c_p[2] Not Applicable AY6 fmca_dp_m2c_n[2] AV5 fmca_dp_m2c_p[3] AV6 fmca_dp_m2c_n[3] Merging of Reconfiguration Interfaces XCVR_RECONFIG_GROUP Enable Enable Enable Table 27. Pin Assignments for Bitec FMC Revision 11 DisplayPort Pin Location ( Intel® Arria® 10 Development Kit)
Four Lanes Two Lanes One Lane Source BC7 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] BC8 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] BD5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not applicable BD6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1] BB5 fmca_dp_c2m_p[2] Not applicable BB6 fmca_dp_c2m_n[2] BC3 fmca_dp_c2m_p[3] BC4 fmca_dp_c2m_n[3] Sink AW7 fmca_dp_m2c_p[0] Not applicable Not applicable AW8 fmca_dp_m2c_n[0] BA7 fmca_dp_m2c_p[1] BA8 fmca_dp_m2c_n[1] AY5 fmca_dp_m2c_p[2] fmca_dp_m2c_p[0] AY6 fmca_dp_m2c_n[2] fmca_dp_m2c_n[0] AV5 fmca_dp_m2c_p[3] fmca_dp_m2c_p[1] fmca_dp_m2c_p[0] AV6 fmca_dp_m2c_n[3] fmca_dp_m2c_n[1] fmca_dp_m2c_n[0] Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable Note: You can disable the non-applicable pin assignments in the Assignment Editor.