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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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2.3. Enabling Adaptive Sync Support
To enable support for the Adaptive Sync feature in the design examples without PCR, you need to edit the MSA_TIMING_PAR_IGNORED bit of the DPCD 00007h register and the MSA_TIMING_PAR_IGNORE_EN bit of the DPCD 00107h register in the rx_utils.c file in the software folder.
Note: The Adaptive Sync feature is applicable only when you turn on the Enable GPU control parameter.
To edit the bits:
- Locate data[7] = 0x80; // DPCD_ADDR_DOWN_STREAM_PORT_COUNT.
- Change 0x80 to 0xC0.
- Locate data[7] = 0x00; // DPCD_ADDR_DOWNSPREAD_CTRL
- Change 0x00 to 0x80.
- Regenerate the ELF file, refer to Regenerating ELF File.
- After programming the SOF file into the FPGA, program the updated ELF file into the FPGA.