DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 2/01/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Intel® Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Intel® Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

1.6. DisplayPort Intel® FPGA IP Design Example Parameters

Table 6.   DisplayPort Intel® FPGA IP Design Example Parameters for Intel® Arria® 10 Devices

Parameter

Value

Description

Available Design Example
Select Design
  • None
  • DisplayPort SST TX-only
  • DisplayPort SST RX-only
  • DisplayPort SST Parallel Loopback with PCR
  • DisplayPort SST Parallel Loopback without PCR
  • DisplayPort MST Parallel Loopback with PCR
  • DisplayPort MST Parallel Loopback without PCR
 Select the design example to be generated.
  • None: No design example is available for the current parameter selection
  • DisplayPort SST TX-only: This design example demonstrates the transmission of a single video stream with a fixed pattern resolution (1920x1080 60Hz) using the Test Pattern Generator II.
  • DisplayPort SST RX-only: This design example demonstrates the transmission of a single video stream from the DisplayPort sink with the Pixel Clock Recovery (PCR).
  • DisplayPort SST Parallel Loopback with PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source through a Pixel Clock Recovery (PCR) module when you turn off the Enable Video Input Image Port parameter.
  • DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
  • DisplayPort MST Parallel Loopback with PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source through a Pixel Clock Recovery (PCR) module when you turn off the Enable Video Input Image Port parameter and turn on the Support MST parameter for TX and RX.
  • DisplayPort MST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter and turn on the Support MST parameter for TX and RX.
Note: Only DisplayPort SST Parallel Loopback with PCR is available in the Intel® Quartus® Prime Standard Edition.
Design Example Files
Simulation

On, Off

Turn on this option to generate the necessary files for the simulation testbench.
Synthesis

On, Off

Turn on this option to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration.

Generated HDL Format
Generate File Format

Verilog, VHDL

 Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.

Target Development Kit

Select Board
  • No Development Kit
  • Intel® Arria® 10 GX FPGA Development Kit
  • Custom Development Kit
 Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Intel® Arria® 10 GX FPGA Development Kit: This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
Level Two Title