DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 2/01/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Intel® Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Intel® Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

1.1. Directory Structure

The directories contain the generated files for the DisplayPort design example.
Figure 2. Directory Structure for the Design Example
Table 1.  Other Generated Files in RTL Folder
Folders Files
clkrec /altera_pll_reconfig_core.v
/altera_pll_reconfig_mif_reader.v
/altera_pll_reconfig_top.v
/bitec_clkrec.qip
/bitec_clkrec.sdc
/bitec_clkrec.v
/bitec_dp_add.v
/bitec_dp_cdc.v
/bitec_dp_cdc_fifo.v
/bitec_dp_cdc_pulse.v
/bitec_dp_cnt.v
/bitec_dp_dcfifo.v
/bitec_dp_dd.v
/bitec_dp_div.v
/bitec_dp_mult.v
/bitec_fpll_calc.v
/bitec_fpll_cntrl.v
/bitec_fpll_reconf.v
/bitec_loop_cntrl.v
/bitec_vsyngen.v
  • /clkrec_pll135_a10.qsys ( Intel® Quartus® Prime Standard Edition)
  • /clkrec_pll135_a10.ip ( Intel® Quartus® Prime Pro Edition)
  • /clkrec_pll_a10.qsys ( Intel® Quartus® Prime Standard Edition)
  • /clkrec_pll1_a10.ip ( Intel® Quartus® Prime Pro Edition)
  • /clkrec_reset_a10.qsys ( Intel® Quartus® Prime Standard Edition)
  • /clkrec_reset_a10.ip ( Intel® Quartus® Prime Pro Edition)
<Platform Designer generated folder>
core
  • /dp_core.qsys ( Intel® Quartus® Prime Standard Edition)
  • /dp_core.ip ( Intel® Quartus® Prime Pro Edition)
  • /dp_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /dp_rx.ip ( Intel® Quartus® Prime Pro Edition)
  • /dp_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /dp_tx.ip ( Intel® Quartus® Prime Pro Edition)
<Platform Designer generated folder>
rx_phy
  • /gxb_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_rx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx_reset.ip ( Intel® Quartus® Prime Pro Edition)
/rx_phy_top.v
<Platform Designer generated folder>
tx_phy
  • /gxb_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_reset.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_fpll.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_fpll.ip ( Intel® Quartus® Prime Pro Edition)
/tx_phy_top.v
<Platform Designer generated folder>
Table 2.   Other Generated Files in Simulation Folder
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
<cds_libs folder>
core
  • /dp_core.qsys ( Intel® Quartus® Prime Standard Edition)
  • /dp_core.ip ( Intel® Quartus® Prime Pro Edition)
  • /dp_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /dp_rx.ip ( Intel® Quartus® Prime Pro Edition)
  • /dp_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /dp_tx.ip ( Intel® Quartus® Prime Pro Edition)
<Platform Designer generated folder>
mentor /mentor.do
/msim_setup.tcl
rx_phy
  • /gxb_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx.ip ( Intel® Quartus® Prime Pro Edition)
/rx_phy_top.v
  • /gxb_rx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx_reset.ip ( Intel® Quartus® Prime Pro Edition)
<Platform Designer generated folder>
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench /a10_dp_harness.sv
/clk_gen.v
/freq_check.v
/rx_freq_check.v
/tx_freq_check.v
/vga_driver.v
tx_phy
  • /gxb_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx.ip ( Intel® Quartus® Prime Pro Edition)
<Platform Designer generated folder>
  • /gxb_tx_fpll.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_fpll.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_reset.ip ( Intel® Quartus® Prime Pro Edition)
/tx_phy_top.v
xcelium /cds.lib
/hdl.var
/xcelium_sim.sh
/xcelium_setup.sh
<cds_libs folder>
Level Two Title