Visible to Intel only — GUID: owi1637202419838
Ixiasoft
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
Visible to Intel only — GUID: owi1637202419838
Ixiasoft
2.4.1. Intel® Arria® 10 DisplayPort SST TX-only Design Features
The TX-only design example demonstrates the transmission of a single video stream with a fixed pattern resolution (1920x1080 60Hz) using the Test Pattern Generator II.
Figure 9. Intel® Arria® 10 DisplayPort TX-only Design
- To generate TX-only design, turn on DisplayPort source's parameter, TX_SUPPORT_DP, and turn off DisplayPort sink's parameter, RX_SUPPORT_DP.
- In this variant, the DisplayPort source's parameter, TX_SUPPORT_IM_ENABLE, is turned off and the standard VSYNC/HSYNC/DE video interface is used.
- Test Pattern Generator II (TPG II) and Clocked Video Output II (CVO II) are integrated as video source to display 1080p60 color bar image.
- The IOPLL drives the video clock at a 160 MHz to CVO II and 37.125 MHz (4 pixel per clock) to TPG II.
Note: Update the Test Pattern Generator II to lower resolution if the existing Resolution does not fit in to the configured Max Link Rate and Max Lane Count.