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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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3.4.3.2.2. Key Programmer
To program the encrypted HDCP production keys onto the EEPROM, follow these steps:
- Copy the key programmer design files from the following path to your working directory: <IP Root Directory>/hdcp2x/hw_demo/key_programmer/<Device Family Name>
- Copy the software header file (hdcp_key<Number>.h) generated from the KEYENC software utility (section Encrypt Single Key for Single EEPROM) to the software/key_programmer_src/ directory and rename it as hdcp_key.h.
- Run ./runall.tcl. This script executes the following commands:
- Generate IP catalog files
- Generate the Platform Designer system
- Create an Intel® Quartus® Prime project
- Create a software workspace and build the software
- Perform a full compilation
- Download the Software Object File (.sof) to the FPGA to program the encrypted HDCP production keys onto the EEPROM.
Generate the DisplayPort SST Parallel Loopback With PCR design example with Support HDCP 2.3 and Support HDCP 1.3 parameters turned on, then follow the following step to include the HDCP protection key.
- Copy the mif file (hdcp_kmem.mif) generated from the KEYENC software utility (section Encrypt N Keys for N EEPROMs) to the <project directory>/quartus/hdcp/ directory.