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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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3.4. Design Walkthrough
Setting up and running the HDCP over DisplayPort design example consists of five stages.
- Set up the hardware.
- Generate the design.
- Edit the HDCP key memory files to include your HDCP production keys.
- Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0)
- Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
- Compile the design.
- View the results.