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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Intel® Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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1.4. Simulating the Design
The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
- Navigate to the simulation folder of your choice.
- Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
- Analyze the results.
Table 3. Steps to Run Simulation Simulator Working Directory Instructions Riviera-PRO* /simulation/aldec In the command line, typevsim -c -do aldec.do
ModelSim* /simulation/mentor In the command line, typevsim -c -do mentor.do
Xcelium* /simulation/xcelium In the command line, typesource xcelium.sh
VCS* /simulation/synopsys/vcs In the command line, typesource vcs_sim.sh
VCS* MX /simulation/synopsys/vcsmx In the command line, typesource vcsmx_sim.sh
A successful simulation ends with the following message:# SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c, # SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c, # Pass: Test Completed