Arria® V Device Datasheet

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ID 683022
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
1. Arria® V GX, GT, SX, and ST Device Datasheet 2. Arria V GZ Device Datasheet
1. Arria® V GX, GT, SX, and ST Device Datasheet x
1.1. Electrical Characteristics 1.2. Switching Characteristics 1.3. Configuration Specifications 1.4. I/O Timing 1.5. Glossary 1.6. Arria® V GX, GT, SX, and ST Device Datasheet Revision History
1.1. Electrical Characteristics x
1.1.1. Operating Conditions
1.1.1. Operating Conditions x
1.1.1.1. Absolute Maximum Ratings 1.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 1.1.1.3. Recommended Operating Conditions 1.1.1.4. DC Characteristics 1.1.1.5. I/O Standard Specifications
1.1.1.3. Recommended Operating Conditions x
1.1.1.3.1. Recommended Operating Conditions 1.1.1.3.2. Transceiver Power Supply Operating Conditions 1.1.1.3.3. HPS Power Supply Operating Conditions
1.1.1.4. DC Characteristics x
1.1.1.4.1. Supply Current and Power Consumption 1.1.1.4.2. I/O Pin Leakage Current 1.1.1.4.3. Bus Hold Specifications 1.1.1.4.4. OCT Calibration Accuracy Specifications 1.1.1.4.5. OCT Without Calibration Resistance Tolerance Specifications 1.1.1.4.6. OCT Variation after Power-Up Calibration 1.1.1.4.7. Pin Capacitance 1.1.1.4.8. Hot Socketing 1.1.1.4.9. Internal Weak Pull-Up Resistor
1.1.1.5. I/O Standard Specifications x
1.1.1.5.1. Single-Ended I/O Standards 1.1.1.5.2. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications 1.1.1.5.3. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 1.1.1.5.4. Differential SSTL I/O Standards 1.1.1.5.5. Differential HSTL and HSUL I/O Standards 1.1.1.5.6. Differential I/O Standard Specifications
1.2. Switching Characteristics x
1.2.1. Transceiver Performance Specifications 1.2.2. Core Performance Specifications 1.2.3. Periphery Performance 1.2.4. HPS Specifications
1.2.1. Transceiver Performance Specifications x
1.2.1.1. Transceiver Specifications for Arria V GX and SX Devices 1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices 1.2.1.3. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.5. Typical TX VOD Setting for Arria® V Transceiver Channels with termination of 100 Ω 1.2.1.6. Transmitter Pre-Emphasis Levels 1.2.1.7. Transceiver Compliance Specification
1.2.2. Core Performance Specifications x
1.2.2.1. Clock Tree Specifications 1.2.2.2. PLL Specifications 1.2.2.3. DSP Block Performance Specifications 1.2.2.4. Memory Block Performance Specifications 1.2.2.5. Internal Temperature Sensing Diode Specifications
1.2.3. Periphery Performance x
1.2.3.1. High-Speed I/O Specifications 1.2.3.2. DPA Lock Time Specifications 1.2.3.3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications 1.2.3.4. DLL Frequency Range Specifications 1.2.3.5. DQS Logic Block Specifications 1.2.3.6. Memory Output Clock Jitter Specifications 1.2.3.7. OCT Calibration Block Specifications 1.2.3.8. Duty Cycle Distortion (DCD) Specifications
1.2.4. HPS Specifications x
1.2.4.1. HPS Clock Performance 1.2.4.2. HPS PLL Specifications 1.2.4.3. Quad SPI Flash Timing Characteristics 1.2.4.4. SPI Timing Characteristics 1.2.4.5. SD/MMC Timing Characteristics 1.2.4.6. USB Timing Characteristics 1.2.4.7. Ethernet Media Access Controller (EMAC) Timing Characteristics 1.2.4.8. I2C Timing Characteristics 1.2.4.9. NAND Timing Characteristics 1.2.4.10. Arm* Trace Timing Characteristics 1.2.4.11. UART Interface 1.2.4.12. GPIO Interface 1.2.4.13. HPS JTAG Timing Specifications
1.2.4.2. HPS PLL Specifications x
1.2.4.2.1. HPS PLL VCO Frequency Range 1.2.4.2.2. HPS PLL Input Clock Range 1.2.4.2.3. HPS PLL Input Jitter
1.3. Configuration Specifications x
1.3.1. POR Specifications 1.3.2. FPGA JTAG Configuration Timing 1.3.3. FPP Configuration Timing 1.3.4. Active Serial (AS) Configuration Timing 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme 1.3.6. Passive Serial (PS) Configuration Timing 1.3.7. Initialization 1.3.8. Configuration Files 1.3.9. Minimum Configuration Time Estimation 1.3.10. Remote System Upgrades 1.3.11. User Watchdog Internal Oscillator Frequency Specifications
1.3.3. FPP Configuration Timing x
1.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 1.3.3.2. FPP Configuration Timing when DCLK-to-DATA[] = 1 1.3.3.3. FPP Configuration Timing when DCLK-to-DATA[] >1
1.4. I/O Timing x
1.4.1. Programmable IOE Delay 1.4.2. Programmable Output Buffer Delay
2. Arria V GZ Device Datasheet x
2.1. Electrical Characteristics 2.2. Switching Characteristics 2.3. Configuration Specification 2.4. I/O Timing 2.5. Glossary 2.6. Arria® V GZ Device Datasheet Revision History
2.1. Electrical Characteristics x
2.1.1. Operating Conditions
2.1.1. Operating Conditions x
2.1.1.1. Absolute Maximum Ratings 2.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 2.1.1.3. Recommended Operating Conditions 2.1.1.4. DC Characteristics 2.1.1.5. I/O Standard Specifications
2.1.1.3. Recommended Operating Conditions x
2.1.1.3.1. Recommended Transceiver Power Supply Operating Conditions 2.1.1.3.2. Transceiver Power Supply Requirements
2.1.1.4. DC Characteristics x
2.1.1.4.1. Supply Current 2.1.1.4.2. Power Consumption 2.1.1.4.3. I/O Pin Leakage Current 2.1.1.4.4. Bus Hold Specifications 2.1.1.4.5. On-Chip Termination (OCT) Specifications 2.1.1.4.6. Pin Capacitance 2.1.1.4.7. Hot Socketing 2.1.1.4.8. Internal Weak Pull-Up Resistor
2.2. Switching Characteristics x
2.2.1. Transceiver Performance Specifications 2.2.2. Core Performance Specifications 2.2.3. Periphery Performance
2.2.1. Transceiver Performance Specifications x
2.2.1.1. Reference Clock 2.2.1.2. Transceiver Clocks 2.2.1.3. Receiver 2.2.1.4. Transmitter 2.2.1.5. CMU PLL 2.2.1.6. ATX PLL 2.2.1.7. Fractional PLL 2.2.1.8. Clock Network Data Rate 2.2.1.9. Standard PCS Data Rate 2.2.1.10. 10G PCS Data Rate 2.2.1.11. Typical VOD Settings
2.2.2. Core Performance Specifications x
2.2.2.1. Clock Tree Specifications 2.2.2.2. PLL Specifications 2.2.2.3. DSP Block Specifications 2.2.2.4. Memory Block Specifications 2.2.2.5. Temperature Sensing Diode Specifications
2.2.3. Periphery Performance x
2.2.3.1. High-Speed I/O Specification 2.2.3.2. DLL Range Specifications 2.2.3.3. DQS Logic Block Specifications 2.2.3.4. Memory Output Clock Jitter Specifications 2.2.3.5. OCT Calibration Block Specifications 2.2.3.6. Duty Cycle Distortion (DCD) Specifications
2.2.3.1. High-Speed I/O Specification x
2.2.3.1.1. High-Speed Clock Specifications 2.2.3.1.2. Transmitter High-Speed I/O Specifications 2.2.3.1.3. Receiver High-Speed I/O Specifications 2.2.3.1.4. DPA Mode High-Speed I/O Specifications 2.2.3.1.5. Soft CDR Mode High-Speed I/O Specifications 2.2.3.1.6. Non DPA Mode High-Speed I/O Specifications
2.3. Configuration Specification x
2.3.1. POR Specifications 2.3.2. JTAG Configuration Specifications 2.3.3. Fast Passive Parallel (FPP) Configuration Timing 2.3.4. Active Serial Configuration Timing 2.3.5. Passive Serial Configuration Timing 2.3.6. Initialization 2.3.7. Configuration Files 2.3.8. Remote System Upgrades Circuitry Timing Specification 2.3.9. User Watchdog Internal Oscillator Frequency Specification
2.3.3. Fast Passive Parallel (FPP) Configuration Timing x
2.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 2.3.3.2. FPP Configuration Timing when DCLK to DATA[] = 1 2.3.3.3. FPP Configuration Timing when DCLK to DATA[] > 1
2.4. I/O Timing x
2.4.1. Programmable IOE Delay 2.4.2. Programmable Output Buffer Delay
1. Arria® V GX, GT, SX, and ST Device Datasheet
2. Arria V GZ Device Datasheet

2.2.2.2. PLL Specifications

Table 112.   PLL Specifications for Arria V GZ Devices
Symbol Parameter Min Typ Max Unit
fIN 170 Input clock frequency (C3, I3L speed grade) 5 — 800 MHz
Input clock frequency (C4, I4 speed grade) 5 — 650 MHz
fINPFD Input frequency to the PFD 5 — 325 MHz
fFINPFD Fractional Input clock frequency to the PFD 50 — 160 MHz
fVCO 171 PLL VCO operating range (C3, I3L speed grade) 600 — 1600 MHz
PLL VCO operating range (C4, I4 speed grade) 600 — 1300 MHz
tEINDUTY Input clock or external feedback clock input duty cycle 40 — 60 %
fOUT 172 Output frequency for an internal global or regional clock (C3, I3L speed grade) — — 650 MHz
Output frequency for an internal global or regional clock (C4, I4 speed grade) — — 580 MHz
fOUT_EXT 172 Output frequency for an external clock output (C3, I3L speed grade) — — 667 MHz
Output frequency for an external clock output (C4, I4 speed grade) — — 533 MHz
tOUTDUTY Duty cycle for a dedicated external clock output (when set to 50%) 45 50 55 %
tFCOMP External feedback clock compensation time — — 10 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — 100 MHz
tLOCK Time required to lock from the end-of-device configuration or deassertion of areset — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — 1 ms
fCLBW PLL closed-loop low bandwidth — 0.3 — MHz
PLL closed-loop medium bandwidth — 1.5 — MHz
PLL closed-loop high bandwidth 173 — 4 — MHz
tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps
tARESET Minimum pulse width on the areset signal 10 — — ns
tINCCJ 174, 175 Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz) — — 0.15 UI (p-p)
Input clock cycle-to-cycle jitter (fREF < 100 MHz) -750 — +750 ps (p-p)
tOUTPJ_DC 176 Period Jitter for dedicated clock output in integer PLL (fOUT ≥ 100 MHz) — — 175 ps (p-p)
Period Jitter for dedicated clock output in integer PLL (fOUT < 100 Mhz) — — 17.5 mUI (p-p)
tFOUTPJ_DC 176 Period Jitter for dedicated clock output in fractional PLL (fOUT ≥ 100 MHz) — — 250179, 
175177 ps (p-p)
Period Jitter for dedicated clock output in fractional PLL (fOUT < 100 MHz) — — 25179,
17.5 177 mUI (p-p)
tOUTCCJ_DC 176 Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT ≥ 100 MHz) — — 175 ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in integer PLL (fOUT < 100 MHz) — — 17.5 mUI (p-p)
tFOUTCCJ_DC 176 Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT ≥ 100 MHz) — — 250179,
175 177 ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in fractional PLL (fOUT < 100 MHz) — — 25179,
17.5 177 mUI (p-p)
tOUTPJ_IO , 176, 178 Period Jitter for a clock output on a regular I/O in integer PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p)
Period Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) — — 60 mUI (p-p)
tFOUTPJ_IO 176, 178, 179 Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p)
Period Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) — — 60 mUI (p-p)
tOUTCCJ_IO 176, 178 Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O in integer PLL (fOUT < 100 MHz) — — 60 mUI (p-p)
tFOUTCCJ_IO 176, 178, 179 Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT ≥ 100 MHz) — — 600 ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O in fractional PLL (fOUT < 100 MHz) — — 60 mUI (p-p)
tCASC_OUTPJ_DC 176, 180 Period Jitter for a dedicated clock output in cascaded PLLs (fOUT ≥ 100 MHz) — — 175 ps (p-p)
Period Jitter for a dedicated clock output in cascaded PLLS (fOUT < 100 MHz) — — 17.5 mUI (p-p)
dKBIT Bit number of Delta Sigma Modulator (DSM) 8 24 32 Bits
kVALUE Numerator of Fraction 128 8388608 2147483648 —
fRES Resolution of VCO frequency (fINPFD = 100 MHz) 390625 5.96 0.023 Hz
Related Information
170 This specification is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
171 The VCO frequency reported by the Intel® Quartus® Prime software in the PLL Usage Summary section of the compilation report takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification.
172 This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
173 High bandwidth PLL settings are not supported in external feedback mode.
174 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
175 The fREF is fIN/N specification applies when N = 1.
176 Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in the Worst-Case DCD on Arria V GZ I/O Pins table.
177 This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
178 The external memory interface clock output jitter specifications use a different measurement method, which is available in the Memory Output Clock Jitter Specification for Arria V GZ Devices table.
179 This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
180 The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz ≤ Upstream PLL BW < 1 MHz 
b. Downstream PLL: Downstream PLL BW > 2 MHz
Level Two Title