Arria® V Device Datasheet

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ID 683022
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
1. Arria® V GX, GT, SX, and ST Device Datasheet 2. Arria V GZ Device Datasheet
1. Arria® V GX, GT, SX, and ST Device Datasheet x
1.1. Electrical Characteristics 1.2. Switching Characteristics 1.3. Configuration Specifications 1.4. I/O Timing 1.5. Glossary 1.6. Arria® V GX, GT, SX, and ST Device Datasheet Revision History
1.1. Electrical Characteristics x
1.1.1. Operating Conditions
1.1.1. Operating Conditions x
1.1.1.1. Absolute Maximum Ratings 1.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 1.1.1.3. Recommended Operating Conditions 1.1.1.4. DC Characteristics 1.1.1.5. I/O Standard Specifications
1.1.1.3. Recommended Operating Conditions x
1.1.1.3.1. Recommended Operating Conditions 1.1.1.3.2. Transceiver Power Supply Operating Conditions 1.1.1.3.3. HPS Power Supply Operating Conditions
1.1.1.4. DC Characteristics x
1.1.1.4.1. Supply Current and Power Consumption 1.1.1.4.2. I/O Pin Leakage Current 1.1.1.4.3. Bus Hold Specifications 1.1.1.4.4. OCT Calibration Accuracy Specifications 1.1.1.4.5. OCT Without Calibration Resistance Tolerance Specifications 1.1.1.4.6. OCT Variation after Power-Up Calibration 1.1.1.4.7. Pin Capacitance 1.1.1.4.8. Hot Socketing 1.1.1.4.9. Internal Weak Pull-Up Resistor
1.1.1.5. I/O Standard Specifications x
1.1.1.5.1. Single-Ended I/O Standards 1.1.1.5.2. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications 1.1.1.5.3. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 1.1.1.5.4. Differential SSTL I/O Standards 1.1.1.5.5. Differential HSTL and HSUL I/O Standards 1.1.1.5.6. Differential I/O Standard Specifications
1.2. Switching Characteristics x
1.2.1. Transceiver Performance Specifications 1.2.2. Core Performance Specifications 1.2.3. Periphery Performance 1.2.4. HPS Specifications
1.2.1. Transceiver Performance Specifications x
1.2.1.1. Transceiver Specifications for Arria V GX and SX Devices 1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices 1.2.1.3. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.5. Typical TX VOD Setting for Arria® V Transceiver Channels with termination of 100 Ω 1.2.1.6. Transmitter Pre-Emphasis Levels 1.2.1.7. Transceiver Compliance Specification
1.2.2. Core Performance Specifications x
1.2.2.1. Clock Tree Specifications 1.2.2.2. PLL Specifications 1.2.2.3. DSP Block Performance Specifications 1.2.2.4. Memory Block Performance Specifications 1.2.2.5. Internal Temperature Sensing Diode Specifications
1.2.3. Periphery Performance x
1.2.3.1. High-Speed I/O Specifications 1.2.3.2. DPA Lock Time Specifications 1.2.3.3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications 1.2.3.4. DLL Frequency Range Specifications 1.2.3.5. DQS Logic Block Specifications 1.2.3.6. Memory Output Clock Jitter Specifications 1.2.3.7. OCT Calibration Block Specifications 1.2.3.8. Duty Cycle Distortion (DCD) Specifications
1.2.4. HPS Specifications x
1.2.4.1. HPS Clock Performance 1.2.4.2. HPS PLL Specifications 1.2.4.3. Quad SPI Flash Timing Characteristics 1.2.4.4. SPI Timing Characteristics 1.2.4.5. SD/MMC Timing Characteristics 1.2.4.6. USB Timing Characteristics 1.2.4.7. Ethernet Media Access Controller (EMAC) Timing Characteristics 1.2.4.8. I2C Timing Characteristics 1.2.4.9. NAND Timing Characteristics 1.2.4.10. Arm* Trace Timing Characteristics 1.2.4.11. UART Interface 1.2.4.12. GPIO Interface 1.2.4.13. HPS JTAG Timing Specifications
1.2.4.2. HPS PLL Specifications x
1.2.4.2.1. HPS PLL VCO Frequency Range 1.2.4.2.2. HPS PLL Input Clock Range 1.2.4.2.3. HPS PLL Input Jitter
1.3. Configuration Specifications x
1.3.1. POR Specifications 1.3.2. FPGA JTAG Configuration Timing 1.3.3. FPP Configuration Timing 1.3.4. Active Serial (AS) Configuration Timing 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme 1.3.6. Passive Serial (PS) Configuration Timing 1.3.7. Initialization 1.3.8. Configuration Files 1.3.9. Minimum Configuration Time Estimation 1.3.10. Remote System Upgrades 1.3.11. User Watchdog Internal Oscillator Frequency Specifications
1.3.3. FPP Configuration Timing x
1.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 1.3.3.2. FPP Configuration Timing when DCLK-to-DATA[] = 1 1.3.3.3. FPP Configuration Timing when DCLK-to-DATA[] >1
1.4. I/O Timing x
1.4.1. Programmable IOE Delay 1.4.2. Programmable Output Buffer Delay
2. Arria V GZ Device Datasheet x
2.1. Electrical Characteristics 2.2. Switching Characteristics 2.3. Configuration Specification 2.4. I/O Timing 2.5. Glossary 2.6. Arria® V GZ Device Datasheet Revision History
2.1. Electrical Characteristics x
2.1.1. Operating Conditions
2.1.1. Operating Conditions x
2.1.1.1. Absolute Maximum Ratings 2.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 2.1.1.3. Recommended Operating Conditions 2.1.1.4. DC Characteristics 2.1.1.5. I/O Standard Specifications
2.1.1.3. Recommended Operating Conditions x
2.1.1.3.1. Recommended Transceiver Power Supply Operating Conditions 2.1.1.3.2. Transceiver Power Supply Requirements
2.1.1.4. DC Characteristics x
2.1.1.4.1. Supply Current 2.1.1.4.2. Power Consumption 2.1.1.4.3. I/O Pin Leakage Current 2.1.1.4.4. Bus Hold Specifications 2.1.1.4.5. On-Chip Termination (OCT) Specifications 2.1.1.4.6. Pin Capacitance 2.1.1.4.7. Hot Socketing 2.1.1.4.8. Internal Weak Pull-Up Resistor
2.2. Switching Characteristics x
2.2.1. Transceiver Performance Specifications 2.2.2. Core Performance Specifications 2.2.3. Periphery Performance
2.2.1. Transceiver Performance Specifications x
2.2.1.1. Reference Clock 2.2.1.2. Transceiver Clocks 2.2.1.3. Receiver 2.2.1.4. Transmitter 2.2.1.5. CMU PLL 2.2.1.6. ATX PLL 2.2.1.7. Fractional PLL 2.2.1.8. Clock Network Data Rate 2.2.1.9. Standard PCS Data Rate 2.2.1.10. 10G PCS Data Rate 2.2.1.11. Typical VOD Settings
2.2.2. Core Performance Specifications x
2.2.2.1. Clock Tree Specifications 2.2.2.2. PLL Specifications 2.2.2.3. DSP Block Specifications 2.2.2.4. Memory Block Specifications 2.2.2.5. Temperature Sensing Diode Specifications
2.2.3. Periphery Performance x
2.2.3.1. High-Speed I/O Specification 2.2.3.2. DLL Range Specifications 2.2.3.3. DQS Logic Block Specifications 2.2.3.4. Memory Output Clock Jitter Specifications 2.2.3.5. OCT Calibration Block Specifications 2.2.3.6. Duty Cycle Distortion (DCD) Specifications
2.2.3.1. High-Speed I/O Specification x
2.2.3.1.1. High-Speed Clock Specifications 2.2.3.1.2. Transmitter High-Speed I/O Specifications 2.2.3.1.3. Receiver High-Speed I/O Specifications 2.2.3.1.4. DPA Mode High-Speed I/O Specifications 2.2.3.1.5. Soft CDR Mode High-Speed I/O Specifications 2.2.3.1.6. Non DPA Mode High-Speed I/O Specifications
2.3. Configuration Specification x
2.3.1. POR Specifications 2.3.2. JTAG Configuration Specifications 2.3.3. Fast Passive Parallel (FPP) Configuration Timing 2.3.4. Active Serial Configuration Timing 2.3.5. Passive Serial Configuration Timing 2.3.6. Initialization 2.3.7. Configuration Files 2.3.8. Remote System Upgrades Circuitry Timing Specification 2.3.9. User Watchdog Internal Oscillator Frequency Specification
2.3.3. Fast Passive Parallel (FPP) Configuration Timing x
2.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 2.3.3.2. FPP Configuration Timing when DCLK to DATA[] = 1 2.3.3.3. FPP Configuration Timing when DCLK to DATA[] > 1
2.4. I/O Timing x
2.4.1. Programmable IOE Delay 2.4.2. Programmable Output Buffer Delay
1. Arria® V GX, GT, SX, and ST Device Datasheet
2. Arria V GZ Device Datasheet

1.6. Arria® V GX, GT, SX, and ST Device Datasheet Revision History

Document Version Changes
2023.05.23
  • Updated the absolute VMAX for a receiver pin specifications in the Receiver Specifications for Arria® V GX and SX Devices table.
  • Updated the absolute VMAX for a receiver pin specifications in the Receiver Specifications for Arria® V GT and ST Devices table.
2019.04.26
  • Added a note for Conversion Time in the Internal Temperature Sensing Diode Specifications for Arria® V Devices table.
  • Updated tDH specifications in the AS Timing Parameters for AS ×1 and ×4 Configurations in Arria® V Devices table.
2019.01.25
  • Added Arria® V Devices Overshoot Duration diagram.
  • Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Arria® V Devices table.
  • Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Arria® V Devices table.
    • Updated tDH specifications. These specifications are applicable to the commercial and industrial grade devices.
    • Added note to tCO, tSU, and tDH.
  • Removed PowerPlay text from tool name.
  • Renamed IP cores as per Intel rebranding.
Date Version Changes
December 2016 2016.12.09
  • Updated VICM (AC coupled) specifications in Receiver Specifications for Arria V GX and SX Devices table.
  • Added maximum specification for Td in Management Data Input/Output (MDIO) Timing Requirements for Arria V Devices table.
  • Updated Tinit specifications in the following tables:
    • FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices
    • FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices
    • AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices
    • PS Timing Parameters for Arria V Devices
June 2016 2016.06.10
  • Changed pin capacitance to maximum values.
  • Updated SPI Master Timing Requirements for Arria V Devices table.
    • Added Tsu and Th specifications.
    • Removed Tdinmax specifications.
  • Updated SPI Master Timing Diagram.
  • Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Arria® V Devices table.
December 2015 2015.12.16
  • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices table.
    • Updated Fclk, Tdutycycle, and Tdssfrst specifications.
    • Added Tqspi_clk, Tdin_start, and Tdin_end specifications.
    • Removed Tdinmax specifications.
  • Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Arria V Devices table.
  • Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria V Devices table.
    • Updated T clk to Tsdmmc_clk_out symbol.
    • Updated Tsdmmc_clk_out and Td specifications.
    • Added Tsdmmc_clk, Tsu, and Th specifications.
    • Removed Tdinmax specifications.
  • Updated the following diagrams:
    • Quad SPI Flash Timing Diagram
    • SD/MMC Timing Diagram
  • Updated configuration .rbf sizes for Arria V devices.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.16
  • Added the supported data rates for the following output standards using true LVDS output buffer types in the High-Speed I/O Specifications for Arria® V Devices table:
    • True RSDS output standard: data rates of up to 360 Mbps
    • True mini-LVDS output standard: data rates of up to 400 Mbps
  • Added note in the condition for Transmitter—Emulated Differential I/O Standards fHSDR data rate parameter in the High-Speed I/O Specifications for Arria® V Devices table. Note: When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
  • Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
  • Updated Th location in I2C Timing Diagram.
  • Updated Twp location in NAND Address Latch Timing Diagram.
  • Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria® V Devices table.
  • Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configurations in Arria® V Devices table.
  • Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Arria® V Devices chapter.
    • FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1
    • FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1
    • AS Configuration Timing Waveform
    • PS Configuration Timing Waveform
January 2015 2015.01.30
  • Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply” in the following tables:
    • Absolute Maximum Ratings for Arria® V Devices
    • HPS Power Supply Operating Conditions for Arria® V SX and ST Devices
  • Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
  • Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK phase noise specification.
  • Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design.
  • Updated HPS Clock Performance main_base_clk specifications from 525 MHz (for –I3 speed grade) and 462 MHz (for –C4 speed grade) to 400 MHz.
  • Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C5, –I5, and –C6 speed grades), 1,850 MHz (for –C4 speed grade), and 2,100 MHz (for –I3 speed grade).
  • Changed the symbol for HPS PLL input jitter divide value from NR to N.
  • Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:
    • SPI Master Timing Requirements for Arria® V Devices
    • SPI Slave Timing Requirements for Arria® V Devices
  • Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board.
  • Added HPS JTAG timing specifications.
  • Updated FPGA JTAG timing specifications note as follows: A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V.
  • Updated the value in the VICM (AC Coupled) row and in note 6 from 650 mV to 750 mV in the Transceiver Specifications for Arria® V GT and ST Devices table.
July 2014 3.8
  • Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
  • Updated VCC_HPS specification in Table 5.
  • Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V.
  • Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20 and Table 21.
  • Updated description in “HPS PLL Specifications” section.
  • Updated VCO range maximum specification in Table 39.
  • Updated Td and Th specifications in Table 45.
  • Added Th specification in Table 47 and Figure 13.
  • Updated a note in Figure 20, Figure 21, and Figure 23 as follows: Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required.
  • Removed “Remote update only in AS mode” specification in Table 58.
  • Added DCLK device initialization clock source specification in Table 60.
  • Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature.
  • Removed fMAX_RU_CLK specification in Table 63.
February 2014 3.7
  • Updated VCCRSTCLK_HPS maximum specification in Table 1.
  • Added VCC_AUX_SHARED specification in Table 1.
December 2013 3.6
  • Added “HPS PLL Specifications”.
  • Added Table 24, Table 39, and Table 40.
  • Updated Table 1, Table 3, Table 5, Table 19, Table 20, Table 21, Table 38, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50, Table 51, Table 55, Table 56, and Table 59.
  • Updated Figure 7, Figure 13, Figure 15, Figure 16, and Figure 19.
  • Removed table: GPIO Pulse Width for Arria® V Devices.
August 2013 3.5
  • Removed “Pending silicon characterization” note in Table 29.
  • Updated Table 25.
August 2013 3.4
  • Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 30, Table 31, Table 35, Table 36, Table 51, Table 53, Table 54, Table 55, Table 56, Table 57, Table 60, Table 62, and Table 64.
  • Updated Table 1, Table 3, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, and Table 29.
June 2013 3.3 Updated Table 20, Table 21, Table 25, and Table 38.
May 2013 3.2
  • Added Table 37.
  • Updated Figure 8, Figure 9, Figure 20, Figure 22, and Figure 23.
  • Updated Table 1, Table 5, Table 10, Table 13, Table 19, Table 20, Table 21, Table 23, Table 29, Table 39, Table 40, Table 46, Table 56, Table 57, Table 60, and Table 64.
  • Updated industrial junction temperature range for –I3 speed grade in “PLL Specifications” section.
March 2013 3.1
  • Added HPS reset information in the “HPS Specifications” section.
  • Added Table 60.
  • Updated Table 1, Table 3, Table 17, Table 20, Table 29, and Table 59.
  • Updated Figure 21.
November 2012 3.0
  • Updated Table 2, Table 4, Table 9, Table 14, Table 16, Table 17, Table 20, Table 21, Table 25, Table 29, Table 36, Table 56, Table 57, and Table 60.
  • Removed table: Transceiver Block Jitter Specifications for Arria® V Devices.
  • Added HPS information:
    • Added “HPS Specifications” section.
    • Added Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, and Table 50.
    • Added Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, and Figure 19.
    • Updated Table 3 and Table 5.
October 2012 2.4
  • Updated Arria® V GX VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R minimum and maximum values, and data rate in Table 4.
  • Added receiver VICM (AC coupled) and VICM (DC coupled) values, and transmitter VOCM (AC coupled) and VOCM (DC coupled) values in Table 20 and Table 21.
August 2012 2.3 Updated the SERDES factor condition in Table 30.
July 2012 2.2
  • Updated the maximum voltage for VI (DC input voltage) in Table 1.
  • Updated Table 20 to include the Arria® V GX -I3 speed grade.
  • Updated the minimum value of the fixedclk clock frequency in Table 20 and Table 21.
  • Updated the SERDES factor condition in Table 30.
  • Updated Table 50 to include the IOE programmable delay settings for the Arria® V GX -I3 speed grade.
June 2012 2.1 Updated VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R values in Table 4.
June 2012 2.0
  • Updated for the Quartus® II software v12.0 release:
  • Restructured document.
  • Updated “Supply Current and Power Consumption” section.
  • Updated Table 20, Table 21, Table 24, Table 25, Table 26, Table 35, Table 39, Table 43, and Table 52.
  • Added Table 22, Table 23, and Table 33.
  • Added Figure 1–1 and Figure 1–2.
  • Added “Initialization” and “Configuration Files” sections.
February 2012 1.3
  • Updated Table 2–1.
  • Updated Transceiver-FPGA Fabric Interface rows in Table 2–20.
  • Updated VCCP description.
December 2011 1.2 Updated Table 2–1 and Table 2–3.
November 2011 1.1
  • Updated Table 2–1, Table 2–19, Table 2–26, and Table 2–36.
  • Added Table 2–5.
  • Added Figure 2–4.
August 2011 1.0 Initial release.
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