Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

Download PDF
ID 767853
Date 7/13/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
FPGA Optimization Guide for Intel® oneAPI Toolkits Introduction To FPGA Design Concepts Analyze Your Design Optimize Your Design FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design Methods of Hardware Design How Source Code Becomes a Custom Hardware Datapath Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
FPGA Architecture Overview x
Adaptive Logic Module (ALM) Lookup Table (LUT) Register Digital Signal Processing (DSP) Block Random Access Memory (RAM) Blocks
Concepts of FPGA Hardware Design x
Maximum Frequency (fMAX) Latency Pipelining Throughput Datapath Control Path Occupancy
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Mapping Arrays and Their Accesses to Hardware
Scheduling x
Dynamic Scheduling Clustering the Datapath Handshaking Between Clusters
Mapping Parallelism Models to FPGA Hardware x
Data Parallelism Task Parallelism
Data Parallelism x
Executing Independent Operations Simultaneously Pipelining
Memory Types x
Kernel Memory Global Memory
Analyze Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image
Analyze the FPGA Early Image x
Review the FPGA Optimization Report Access HLD FPGA Reports in JSON Format
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer
Analyze the FPGA Image x
Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL* Applications
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Runtime Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Runtime x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL* Applications x
Set Up the Intercept Layer for OpenCL* Applications
Optimize Your Design x
Throughput Resource Use
Throughput x
Single Work-item Kernels NDRange Kernels Memory Accesses Pipes Host
Single Work-item Kernels x
Single Work-item Kernel Design Guidelines Loops Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Shannonization to Improve FMAX/II Optimize Inner Loop Throughput Improve Loop Performance by Caching On-Chip Memory When is the On-chip Memory Cache Technique Applicable? Implement the On-chip Memory Cache Technique Select the Cache Depth
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Pipes x
Host Pipes
Host Pipes x
Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces
Host x
Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL* Applications
Resource Use x
Data Types and Operations Kernel Variable Accesses
Data Types and Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Integer and Floating-Point Support
Variable-Precision Integer and Floating-Point Support x
Advantages and Limitations of Arbitrary Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for ap_float Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta) FPGA Extensions
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Maximum Throughput Without Area Optimization Heuristics Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
FPGA Extensions x
Pipes Extension Asynchronous Parallelism Within Kernels (task_sequence) device_global Extension (Beta)
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes Pipe and Atomic Fence
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits x
Notices and Disclaimers
FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts
Analyze Your Design
Optimize Your Design
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Improve Loop Performance by Caching On-Chip Memory

In SYCL* task kernels for FPGA, the main objective is to achieve an initiation interval (II) of 1 on performance-critical loops. This means that a new loop iteration is launched on every clock cycle, thereby maximizing the loop's throughput. When the loop contains a loop-carried variable implemented in on-chip memory, the Intel® oneAPI DPC++/C++ Compiler often cannot achieve II=1 because the memory access takes more than one clock cycle. If the updated memory location is necessary on the next loop iteration, the next iteration must be delayed to allow time for the update, hence II > 1.

The on-chip memory cache technique breaks this dependency by storing recently-accessed values in a cache capable of a one-cycle read-modify-write operation. The cache is implemented in FPGA registers rather than on-chip memory. By pulling memory accesses preferentially from the register cache, the loop-carried dependency is broken.

When is the On-chip Memory Cache Technique Applicable?

You can apply the on-chip memory cache technique in the following situations:

  • Failure to achieve II=1 because of a loop-carried memory dependency in on-chip memory

    The on-chip memory cache technique is applicable if the compiler could not pipeline a loop with II=1 because of an on-chip memory dependency. If the compiler could not achieve II=1 because of a global memory dependency, this technique does not apply as the access latencies are too great.

    To check this for a given design, view the Loop Analysis report in the design's optimization report. The Loop Analysis report lists the II of all loops and explains why a lower II is not achievable. Check whether the reason given resembles the compiler failed to schedule this loop with smaller II due to memory dependency. The report describes the most critical loop feedback path during scheduling. Check whether this includes on-chip memory load/store operations on the critical path.

  • An II=1 loop with a load operation of latency 1

    The compiler is capable of reducing the latency of on-chip memory accesses to achieve II=1. In doing so, the compiler makes a trade-off by sacrificing fMAX to improve the II.

    In a design with II=1 critical loops but lower than the desired fMAX, the on-chip memory cache technique might still be applicable. It can help recover fMAX by enabling the compiler to achieve II=1 with a higher latency memory access. To check whether this is the case for a given design, view the Kernel Memory Viewer report in the design's optimization report. Select the desired on-chip memory from the Kernel Memory List, and mouse over the load operation LD to check its latency. If the latency of the load operation is 1, this is a clear sign that the compiler has attempted to sacrifice fMAX to improve loop II.

Implement the On-chip Memory Cache Technique

Consider the FPGA design example in onchip_memory_cache.cpp, which demonstrates the technique using a program that computes a histogram. The histogram operation accepts an input vector of values, separates the values into buckets, and counts the number of values per bucket. For each input value, an output bucket location is determined, and the count for the bucket is incremented. This count is stored in the on-chip memory, and the increment operation requires reading from memory, performing the increment, and storing the result. This read-modify-write operation is the critical path that can result in II > 1.

To reduce II, the idea is to store recently-accessed values in an FPGA register-implemented cache that is capable of a one-cycle read-modify-write operation. If the memory location required on a given iteration exists in the cache, it is pulled from there. The updated count is written back to both the cache and the on-chip memory. The ivdep attribute is added to inform the compiler that if a loop-carried variable (namely, the variable storing the histogram output) is required within CACHE_DEPTH iterations, it is guaranteed to be available right away.

Select the Cache Depth

While any value of CACHE_DEPTH results in functional hardware, the ideal value of CACHE_DEPTH requires some experimentation. The depth of the cache must roughly cover the latency of the on-chip memory access. To determine the correct value, Intel® recommends starting with a value of 2 and then increase it until both II = 1 and load latency > 1. In the onchip_memory_cache.cpp example, a CACHE_DEPTH of 5 is necessary. It is important to find the minimal value of CACHE_DEPTH that results in a maximal performance increase. Unnecessarily large values of CACHE_DEPTH consume unnecessary FPGA resources and can reduce fMAX. Therefore, at a CACHE_DEPTH that results in II=1 and load latency = 1, if further increases to CACHE_DEPTH show no improvement, do not increase CACHE_DEPTH any further.

NOTE:

For additional information, refer to the FPGA tutorial sample Onchip Memory Cache listed in the Intel® oneAPI Samples Browser on Linux* or Windows*, or access the code sample in GitHub.

Parent topic: Loops
Level Two Title