Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

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ID 767853
Date 7/13/2023
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Document Table of Contents
Document Table of Contents x
FPGA Optimization Guide for Intel® oneAPI Toolkits Introduction To FPGA Design Concepts Analyze Your Design Optimize Your Design FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design Methods of Hardware Design How Source Code Becomes a Custom Hardware Datapath Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
FPGA Architecture Overview x
Adaptive Logic Module (ALM) Lookup Table (LUT) Register Digital Signal Processing (DSP) Block Random Access Memory (RAM) Blocks
Concepts of FPGA Hardware Design x
Maximum Frequency (fMAX) Latency Pipelining Throughput Datapath Control Path Occupancy
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Mapping Arrays and Their Accesses to Hardware
Scheduling x
Dynamic Scheduling Clustering the Datapath Handshaking Between Clusters
Mapping Parallelism Models to FPGA Hardware x
Data Parallelism Task Parallelism
Data Parallelism x
Executing Independent Operations Simultaneously Pipelining
Memory Types x
Kernel Memory Global Memory
Analyze Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image
Analyze the FPGA Early Image x
Review the FPGA Optimization Report Access HLD FPGA Reports in JSON Format
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer
Analyze the FPGA Image x
Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL* Applications
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Runtime Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Runtime x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL* Applications x
Set Up the Intercept Layer for OpenCL* Applications
Optimize Your Design x
Throughput Resource Use
Throughput x
Single Work-item Kernels NDRange Kernels Memory Accesses Pipes Host
Single Work-item Kernels x
Single Work-item Kernel Design Guidelines Loops Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Shannonization to Improve FMAX/II Optimize Inner Loop Throughput Improve Loop Performance by Caching On-Chip Memory
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Pipes x
Host Pipes
Host Pipes x
Host Pipe Declaration Example Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces
Host x
Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL* Applications
Resource Use x
Data Types and Operations Kernel Variable Accesses
Data Types and Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Integer and Floating-Point Support
Variable-Precision Integer and Floating-Point Support x
Advantages and Limitations of Arbitrary Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for ap_float Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta) FPGA Extensions
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Maximum Throughput Without Area Optimization Heuristics Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
FPGA Extensions x
Pipes Extension Asynchronous Parallelism Within Kernels (task_sequence) device_global Extension (Beta)
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes Pipe and Atomic Fence
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits x
Notices and Disclaimers
FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts
Analyze Your Design
Optimize Your Design
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Host Pipe Declaration

Each individual host pipe is a program scope class declaration of the templated pipe class.

Host Pipe Template Parameters

Template Parameter

Definition

Valid Values

Default Values

id

A unique type that identifies the host pipe.

type

None

(must be specified)

type

The data type to be carried by the pipe.

type

None

(must be specified)

min_capacity

The minimum number of words in units of T size that the pipe must be able to store without any being read out.

A minimum capacity is required in some algorithms to avoid deadlock or for performance tuning.

The hardware implementation can include more capacity than this parameter, but not less.

Integer greater than or equal to 0

 0
properties The type of a properties class which contains an unordered list of zero or more properties that augment the semantics of the pipe.

For property types and their descriptions, refer to Table 2.

 See Table 2. See Table 2.

The properties template parameter is the type of a SYCL properties class object, including an unordered list of any of the compile-time properties listed in the following table.

Unspecified properties take on the listed default value.

All of the listed properties are declared in the sycl::ext::intel::experimental name space. The properties class itself is declared in the sycl::ext::oneapi::experimental name space.

In IP Components, each host pipe can be configured as a data interface. You can configure whether it appears as an Avalon streaming interface or whether it is accessed through your component CSR using the protocol template parameter.

You can use other parameters to configure other details of the data interface. For details, refer to Host Pipes RTL Interfaces.

Host Pipe Template Properties

Template Parameter

Definition

Valid Values

Default Values

ready_latency<int>

The number of cycles between when the ready signal is de-asserted and when the pipe can no longer accept new inputs when using the avalon_streaming or avalon_strreaming_uses_ready protocol.

Integer greater than or equal to 0

0

bits_per_symbol<int>

Describes how the data is broken into symbols on the data bus. This value is used only in conjunction with Avalon Packet support.

Data is broken down according to how the first_symbol_in_high_order_bits parameter is set.

Integer greater than or equal to 0

The value must divide evenly by the size of the data type

8

uses_valid<bool>

Controls whether a valid signal is present on the pipe interface. If false, the upstream source must provide valid data on every cycle that ready is asserted.

If set to false, the min_capacity, and ready_latency template parameters must be set to 0.

Boolean

true

first_symbol_in_high_order_bits<bool>

Specifies whether the data symbols in the pipe are in big-endian byte order.

Boolean

false

protocol

Specifies the protocol for the pipe interface.

  • protocol_name::avalon_streaming

    or

    protocol_avalon_streaming

  • protocol_name::avalon_streaming_uses_ready

    or

    protocol_avalon_streaming_uses_ready

  • protocol_name::avalon_mm

    or

    protocol_avalon_mm

  • protocol_name::avalon_mm_uses_ready

    or

    protocol_avalon_mm_uses_ready

 protocol_avalon_streaming_uses_ready

Example Host Pipe Declaration

The following code is an example declaration of a host pipe:

// define at the global scope to improve RTL readability
class MyPipeT;
class AnotherPipeT;

// properties 
using MyPipePropertiesT = 
  decltype(sycl::ext::oneapi::experimental::properties(
           sycl::ext::intel::experimental::bits_per_symbol<4>,
           sycl::ext::intel::experimental::first_symbol_in_high_order_bits<false>);

// a host pipe with alias 
using MyPipeInstance = sycl::ext::intel::experimental::pipe<
    MyPipeT,    // An identifier for the pipe
    int,        // The type of data in the pipe
    8,          // The capacity of the pipe
    MyPipePropertiesT // properties
>;

// a second host pipe with alias
using AnotherPipeInstance = cl::sycl::ext::intel::prototype::pipe<
    AnotherPipeT,    // An identifier for the pipe
    float,        // The type of data in the pipe
    4          // The capacity of the pipe
               // no properties specified means all default property values used
>;

Both pipe declarations use an alias for the full templated pipe class name for convenience, as does the properties type declaration for the first pipe. The first pipe carries an int data type and has a min_capacity value of 8. It also uses two non-default property values for the bits_per_symbol property (4) and the first_symbol_in_high_order_bits property (false). The second pipe carries a float data type and has a min_capacity value of 4. By not specifying the properties template parameter, all properties listed in the properties table assume their default values for this pipe.

Parent topic: Host Pipes
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