AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex® F-Tile Devices

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ID 763505
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and DAC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Summary 1.9. Document Revision History for AN 976: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-Tile Devices
1.4. Interoperability Methodology x
1.4.1. Transmitter Data Link Layer 1.4.2. Transmitter Transport Layer (TL)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices

1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Agilex™ F-tile Devices

The JESD204C Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204C Intel® FPGA IP has been hardware-tested with several selected JESD204C compliant digital-to-analog converter (DAC) devices.

This report highlights the interoperability of the JESD204C Intel® FPGA IP with the AD9081 Mixed Signal Front End (MxFE*) evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.


Section Content
Hardware and Software Requirements
Hardware Setup
System Description
Interoperability Methodology
JESD204C Intel FPGA IP and DAC Configurations
Test Results
Test Result Comments
Summary
Document Revision History for AN 976: JESD204C Intel FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel Agilex F-Tile Devices

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