AN 967: Multiple Device Synchronization in Digital Phased Array System
ID
734485
Date
12/15/2023
Public
1. Introduction
This document provides guidelines for multiple data converters and FPGA devices system synchronization in the Digital Phased Array (DPA) system.
This document focuses on:
- Implementation of JESD204B/C with the deterministic latency
- Clock and SYSREF scheme
- Data transformation in clock domain crossing
- Event trigger synchronization
You must be familiar with JESD204B/C protocol and JESD204B/C Intel® FPGA IP core.
Reference | Description |
---|---|
JESD204B Intel® FPGA IP User Guide | Provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7, Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix® V devices. |
JESD204C Intel® FPGA IP User Guide | Provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7, and Intel® Stratix® 10 devices. |
F-Tile JESD204C Intel® FPGA IP User Guide | Provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7 devices. |
F-Tile JESD204B Intel® FPGA IP User Guide | Provides the features, usage guidelines, and detailed description about the design examples for the F-Tile JESD204B Intel® FPGA IP using Intel Agilex® 7 devices. |
AN 433: Constraining and Analyzing Source-Synchronous Interfaces | Describes techniques for constraining and analyzing source-synchronous interfaces. |
Acronym | Expansion |
---|---|
ADC | Analog to Digital Data Converter |
AIB | Advanced Interface Bus |
DPA | Digital Phased Array |
DDR | Double Data Rate |
FIFO | First-In-First-Out |
I/O | Input/Output |
IOE | Input/Output Element |
PA | Phased Array |
PCB | Printed Circuit Board |
PVT | Process, Voltage and Temperature |
RX | Receiver |
TX | Transmitter |