AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

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Date 2/06/2020
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Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core x
ADC- Intel® Arria® 10 Multi-Link Design Overview ADC- Intel® Arria® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Arria® 10 Multi-Link Unsynchronized ADC- Intel® Arria® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Arria® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Arria® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core

Synchronized ADC- Intel® Arria® 10 Multi-Link

To synchronize multiple RX IP cores within the Intel® Arria® 10 device, connect the dev_lane_aligned signal from each IP core with an AND gate. The output of the AND gate connects to the alldev_lane_aligned port of each IP core. The IP cores need to be out of reset simultaneously to complete the link initialization sequence. Multiple IP cores are put into the same JESD204B subsystem so that each IP core’s reset is released by the same reset sequencer simultaneously.

Table 1.  IP Core Ports Connection Summary Table summarizes the IP core ports connection for each Subclass in the multi-link ADCs- Intel® Arria® 10 interfaces for multi-device synchronization.
Subclass SYNC_N (ADC-FPGA) alldev_lane_aligned Reset Remark
0 Combined ANDed and re-distribute Simultaneous Refer to Figure 3
1 Combined or Non-combined Refer to Figure 3 and Figure 4
2

The SYNC_N signal can be combined or separated within the FPGA. Combining the SYNC_N is mandatory for Subclass 0 subsystem. This is to enable the ADCs to transmit initial lane alignment sequence simultaneously.

For Subclass 1, the SYSREF pulse is the timing reference for the entire JESD204B subsystem. The rise of SYNC_N signals and the transition from code group synchronization (CGS) to initial lane alignment sequence (ILAS) is controlled by the SYSREF. It is important to phase-aligned the SYSREF pulses to the FPGA and converters. Combining SYNC_N is not mandatory unless there is a huge skew beyond one Local Multi-Frame Clock (LMFC) period between the SYNC_N signals to the ADCs.

For Subclass 2, the SYNC_N can be separated and the phase adjustment is between each ADC and IP core pair. Combining SYNC_N has the advantage of ensuring the rise of SYNC_N reaches ADCs at the same time.

Note: For Subclass 0 and Subclass 2 IP cores, you can connect the sysref port to ground
Figure 3. Multi-Link Use Case of Synchronized ADCs and FPGA with Combined SYNC_N
Figure 4. Multi-Link Use Case of Synchronized ADCs and FPGA with Non-combined SYNC_N
Figure 5. Clock and Reset Scheme of The Synchronized Multi-link
Note: To add JESD204B IP cores for interfacing with more than one ADC, modifications are needed to the Platform Designer system and top-level HDL of the design example.

Section Content
Design Simulation Guidelines
Design Synthesis Guidelines

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