AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report

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ID 683294
Date 6/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 GX FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and AD9625 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 712 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report

1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report

The Altera® JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) devices.

This report highlights the interoperability of the JESD204B IP core with the AD9625 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.


Section Content
Hardware Requirements
Hardware Setup for Stratix V Advanced Systems Development Kit
Hardware Setup for Arria 10 GX FPGA Development Kit
Hardware Checkout Methodology
JESD204B IP Core and AD9625 Configurations
Test Results
Test Result Comments
AN 712 Document Revision History

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