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6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus® Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex®
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
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1. Introduction to Agilex™ 5 Device Design Guidelines
Updated for: |
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Intel® Quartus® Prime Design Suite 24.1 |
These device design guidelines provide guidance, recommendations, and design considerations to use with Agilex™ 5. This document assists you with the design planning and early system design. The guidelines presented in this document can improve productivity and help avoid common design pitfalls.
This document does not include all Agilex™ 5 device details and features. For more information, refer to the following documents:
- Agilex™ 5 FPGAs and SoCs Device Overview
- Agilex™ 5 FPGAs and SoCs Device Data Sheet
- Agilex™ 5 Product page
- Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs