Device Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813741
Date 4/01/2024
Public
Document Table of Contents

1. Introduction to Agilex™ 5 Device Design Guidelines

Updated for:
Intel® Quartus® Prime Design Suite 24.1

These device design guidelines provide guidance, recommendations, and design considerations to use with Agilex™ 5. This document assists you with the design planning and early system design. The guidelines presented in this document can improve productivity and help avoid common design pitfalls.

This document does not include all Agilex™ 5 device details and features. For more information, refer to the following documents:
  • Agilex™ 5 FPGAs and SoCs Device Overview
  • Agilex™ 5 FPGAs and SoCs Device Data Sheet
  • Agilex™ 5 Product page
  • Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs