qspiregs Summary

Base Address: 0xFF809000

Register Address Offset	Bit Fields
`i_qspi_qspiregs`
`cfg` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`idle` `RO 0x1`	`config_resv2_fld` `RO 0x0`								`bauddiv` `RW 0xF`				`enterxipimm` `RW 0x0`	`enterxipnextrd` `RW 0x0`	`enahbremap` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`endma` `RW 0x0`	`wp` `RW 0x0`	`percslines` `RW 0x0`				`perseldec` `RW 0x0`	`enlegacyip` `RW 0x0`	`endiracc` `RW 0x0`	`config_resv1_fld` `RO 0x0`				`selclkphase` `RW 0x0`	`selclkpol` `RW 0x0`	`en` `RW 0x0`
`devrd` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rd_instr_resv5_fld` `RO 0x0`			`dummyrdclks` `RW 0x0`					`rd_instr_resv4_fld` `RO 0x0`			`enmodebits` `RW 0x0`	`rd_instr_resv3_fld` `RO 0x0`		`datawidth` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rd_instr_resv2_fld` `RO 0x0`		`addrwidth` `RW 0x0`		`rd_instr_resv1_fld` `RO 0x0`		`instwidth` `RW 0x0`		`rdopcode` `RW 0x3`
`devwr` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`wr_instr_resv4_fld` `RO 0x0`			`dummywrclks` `RW 0x0`					`wr_instr_resv3_fld` `RO 0x0`						`datawidth` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wr_instr_resv2_fld` `RO 0x0`		`addrwidth` `RW 0x0`		`wr_instr_resv1_fld` `RO 0x0`				`wropcode` `RW 0x2`
`delay` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`nss` `RW 0x0`								`btwn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`after` `RW 0x0`								`init` `RW 0x0`
`rddatacap` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rd_data_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rd_data_resv_fld` `RO 0x0`											`delay` `RW 0x0`				`byp` `RW 0x1`
`devsz` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`dev_size_resv_fld` `RO 0x0`											`bytespersubsector` `RW 0x10`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`bytesperdevicepage` `RW 0x100`												`numaddrbytes` `RW 0x2`
`srampart` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`resv_fld` `RO 0x0`								`addr` `RW 0x80`
`indaddrtrig` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`addr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`addr` `RW 0x0`
`dmaper` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`dma_periph_resv2_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dma_periph_resv2_fld` `RO 0x0`				`numburstreqbytes` `RW 0x0`				`dma_periph_resv1_fld` `RO 0x0`				`numsglreqbytes` `RW 0x0`
`remapaddr` `0x24`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`modebit` `0x28`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`mode_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`mode_resv_fld` `RO 0x0`								`mode` `RW 0x0`
`sramfill` `0x2C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`indwrpart` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`indrdpart` `RO 0x0`
`txthresh` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`tx_thresh_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tx_thresh_resv_fld` `RO 0x0`												`level` `RW 0x1`
`rxthresh` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rx_thresh_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rx_thresh_resv_fld` `RO 0x0`												`level` `RW 0x1`
`irqstat` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`irq_stat_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`irq_stat_resv_fld` `RO 0x0`			`indsramfull` `RW 0x0`	`rxfull` `RW 0x0`	`rxthreshcmp` `RW 0x0`	`txfull` `RW 0x0`	`txthreshcmp` `RW 0x1`	`rxover` `RW 0x0`	`indxfrlvl` `RW 0x0`	`illegalacc` `RW 0x0`	`protwrattempt` `RW 0x0`	`indrdreject` `RW 0x0`	`indopdone` `RW 0x0`	`underflowdet` `RW 0x0`	`mode_m_fail_fld` `RW 0x0`
`irqmask` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`irq_mask_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`irq_mask_resv_fld` `RO 0x0`			`indsramfull` `RW 0x0`	`rxfull` `RW 0x0`	`rxthreshcmp` `RW 0x0`	`txfull` `RW 0x0`	`txthreshcmp` `RW 0x0`	`rxover` `RW 0x0`	`indxfrlvl` `RW 0x0`	`illegalacc` `RW 0x0`	`protwrattempt` `RW 0x0`	`indrdreject` `RW 0x0`	`indopdone` `RW 0x0`	`underflowdet` `RW 0x0`	`mode_m_fail_mask_fld` `RW 0x0`
`lowwrprot` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`subsector` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`subsector` `RW 0x0`
`uppwrprot` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`subsector` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`subsector` `RW 0x0`
`wrprot` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`wr_prot_ctrl_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wr_prot_ctrl_resv_fld` `RO 0x0`														`en` `RW 0x0`	`inv` `RW 0x0`
`indrd` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`indir_rd_xfer_resv_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`indir_rd_xfer_resv_fld` `RO 0x0`								`num_ind_ops_done` `RO 0x0`		`ind_ops_done_status` `RW 0x0`	`rd_queued` `RO 0x0`	`sram_full` `RW 0x0`	`rd_status` `RO 0x0`	`cancel` `WO 0x0`	`start` `WO 0x0`
`indrdwater` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`level` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`level` `RW 0x0`
`indrdstaddr` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`addr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`addr` `RW 0x0`
`indrdcnt` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`indwr` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`indir_wr_xfer_resv2_fld` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`indir_wr_xfer_resv2_fld` `RO 0x0`								`indcnt` `RO 0x0`		`inddone` `RW 0x0`	`rdqueued` `RO 0x0`	`indir_wr_rsvd_fld` `RO 0x0`	`rdstat` `RO 0x0`	`cancel` `WO 0x0`	`start` `WO 0x0`
`indwrwater` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`level` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`level` `RW 0xFFFFFFFF`
`indwrstaddr` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`addr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`addr` `RW 0x0`
`indwrcnt` `0x7C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`flashcmd` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmdopcode` `RW 0x0`								`enrddata` `RW 0x0`	`numrddatabytes` `RW 0x0`			`encmdaddr` `RW 0x0`	`enmodebit` `RW 0x0`	`numaddrbytes` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`enwrdata` `RW 0x0`	`numwrdatabytes` `RW 0x0`			`numdummybytes` `RW 0x0`					`flash_cmd_cntrl_resv1_fld` `RO 0x0`					`cmdexecstat` `RO 0x0`	`execcmd` `WO 0x0`
`flashcmdaddr` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`addr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`addr` `RW 0x0`
`flashcmdrddatalo` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`data` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`data` `RW 0x0`
`flashcmdrddataup` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`data` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`data` `RW 0x0`
`flashcmdwrdatalo` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`data` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`data` `RW 0x0`
`flashcmdwrdataup` `0xAC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`data` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`data` `RW 0x0`
`moduleid` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`mod_id_resv_fld` `RO 0x0`							`value` `RO 0x1001`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x1001`