flashcmdrddataup

         Device Instruction Configuration Register
Module Instance Base Address Register Address
i_qspi_qspiregs 0xFF809000 0xFF8090A4

Offset: 0xA4

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

data

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

data

RW 0x0

flashcmdrddataup Fields

Bit Name Description Access Reset
31:0 data 
 This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low.
RW 0x0