txthresh
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_qspi_qspiregs | 0xFF809000 | 0xFF809030 |
Offset: 0x30
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
tx_thresh_resv_fld RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
tx_thresh_resv_fld RO 0x0 |
level RW 0x1 |
||||||||||||||
txthresh Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:4 | tx_thresh_resv_fld | RO | 0x0 | |
| 3:0 | level | Defines the level at which the small TX FIFO not full interrupt is generated |
RW | 0x1 |