indrd
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_qspi_qspiregs | 0xFF809000 | 0xFF809060 |
Offset: 0x60
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
indir_rd_xfer_resv_fld RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
indir_rd_xfer_resv_fld RO 0x0 |
num_ind_ops_done RO 0x0 |
ind_ops_done_status RW 0x0 |
rd_queued RO 0x0 |
sram_full RW 0x0 |
rd_status RO 0x0 |
cancel WO 0x0 |
start WO 0x0 |
||||||||
indrd Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:8 | indir_rd_xfer_resv_fld | RO | 0x0 | |||||||
| 7:6 | num_ind_ops_done | This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it. |
RO | 0x0 | ||||||
| 5 | ind_ops_done_status | This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.
|
RW | 0x0 | ||||||
| 4 | rd_queued | Two indirect read operations have been queued
|
RO | 0x0 | ||||||
| 3 | sram_full | SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it."; indirect operation (status)
|
RW | 0x0 | ||||||
| 2 | rd_status | Indirect read operation in progress (status)
|
RO | 0x0 | ||||||
| 1 | cancel | Writing a 1 to this bit will cancel all ongoing indirect read operations.
|
WO | 0x0 | ||||||
| 0 | start | Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation.
|
WO | 0x0 |