rddatacap
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_qspi_qspiregs | 0xFF809000 | 0xFF809010 |
Offset: 0x10
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
rd_data_resv_fld RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rd_data_resv_fld RO 0x0 |
delay RW 0x0 |
byp RW 0x1 |
|||||||||||||
rddatacap Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:5 | rd_data_resv_fld | RO | 0x0 | |||||||
| 4:1 | delay | Delay the read data capturing logic by the programmed number of ref_clk cycles |
RW | 0x0 | ||||||
| 0 | byp | Bypass the adapted loopback clock circuit
|
RW | 0x1 |