irqstat
The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 thru 10 are only valid when legacy SPI mode is active.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_qspi_qspiregs | 0xFF809000 | 0xFF809040 |
Offset: 0x40
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
irq_stat_resv_fld RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
irq_stat_resv_fld RO 0x0 |
indsramfull RW 0x0 |
rxfull RW 0x0 |
rxthreshcmp RW 0x0 |
txfull RW 0x0 |
txthreshcmp RW 0x1 |
rxover RW 0x0 |
indxfrlvl RW 0x0 |
illegalacc RW 0x0 |
protwrattempt RW 0x0 |
indrdreject RW 0x0 |
indopdone RW 0x0 |
underflowdet RW 0x0 |
mode_m_fail_fld RW 0x0 |
||
irqstat Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:13 | irq_stat_resv_fld | RO | 0x0 | |||||||
| 12 | indsramfull | Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation
|
RW | 0x0 | ||||||
| 11 | rxfull | Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full
|
RW | 0x0 | ||||||
| 10 | rxthreshcmp | Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries, 1 : FIFO has >= THRESHOLD entries
|
RW | 0x0 | ||||||
| 9 | txfull | Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full, 1 : FIFO is full
|
RW | 0x0 | ||||||
| 8 | txthreshcmp | Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries, 1 : FIFO has less than THRESHOLD entries
|
RW | 0x1 | ||||||
| 7 | rxover | This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0 : no overflow has been detected. 1 : an overflow has occurred.
|
RW | 0x0 | ||||||
| 6 | indxfrlvl | Indirect Transfer Watermark Level Breached
|
RW | 0x0 | ||||||
| 5 | illegalacc | Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger.
|
RW | 0x0 | ||||||
| 4 | protwrattempt | Write to protected area was attempted and rejected.
|
RW | 0x0 | ||||||
| 3 | indrdreject | Indirect operation was requested but could not be accepted. Two indirect operations already in storage.
|
RW | 0x0 | ||||||
| 2 | indopdone | Controller has completed last triggered indirect operation
|
RW | 0x0 | ||||||
| 1 | underflowdet | 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation This bit is reset only by a system reset and cleared only when the register is read.
|
RW | 0x0 | ||||||
| 0 | mode_m_fail_fld | Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read. 0 : no mode fault has been detected 1 : a mode fault has occurred |
RW | 0x0 |