delay

          This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock.
Module Instance Base Address Register Address
i_qspi_qspiregs 0xFF809000 0xFF80900C

Offset: 0xC

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

nss

RW 0x0

btwn

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

after

RW 0x0

init

RW 0x0

delay Fields

Bit Name Description Access Reset
31:24 nss 
 Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period.
RW 0x0
23:16 btwn 
 Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty.
RW 0x0
15:8 after 
 Delay in QSPI_CLK clocks between the last bit of the current transaction and
    deasserting the device chip select (QSPI_SS). By default (when this field is 0x0), QSPI_SS
    is deasserted on the last falling edge of SCLK_OUT at the completion of the current
    transaction. When this field is programmed with N, QSPI_SS is deasserted N QSPI_CLK clocks after
    the last falling edge of SCLK_OUT.
RW 0x0
7:0 init 
 Delay in master reference clocks between setting n_ss_out low and first bit transfer.
RW 0x0