devrd
Module Instance | Base Address | Register Address |
---|---|---|
i_qspi_qspiregs | 0xFF809000 | 0xFF809004 |
Offset: 0x4
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
rd_instr_resv5_fld RO 0x0 |
dummyrdclks RW 0x0 |
rd_instr_resv4_fld RO 0x0 |
enmodebits RW 0x0 |
rd_instr_resv3_fld RO 0x0 |
datawidth RW 0x0 |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rd_instr_resv2_fld RO 0x0 |
addrwidth RW 0x0 |
rd_instr_resv1_fld RO 0x0 |
instwidth RW 0x0 |
rdopcode RW 0x3 |
devrd Fields
Bit | Name | Description | Access | Reset | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
31:29 | rd_instr_resv5_fld | RO | 0x0 | |||||||||
28:24 | dummyrdclks | Number of dummy clock cycles required by device for read instruction. |
RW | 0x0 | ||||||||
23:21 | rd_instr_resv4_fld | RO | 0x0 | |||||||||
20 | enmodebits | Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.
|
RW | 0x0 | ||||||||
19:18 | rd_instr_resv3_fld | RO | 0x0 | |||||||||
17:16 | datawidth | 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs.
|
RW | 0x0 | ||||||||
15:14 | rd_instr_resv2_fld | RO | 0x0 | |||||||||
13:12 | addrwidth | 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3
|
RW | 0x0 | ||||||||
11:10 | rd_instr_resv1_fld | RO | 0x0 | |||||||||
9:8 | instwidth | 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions, Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions, Address and Data always sent on DQ0, DQ1, DQ2 and DDQ3)
|
RW | 0x0 | ||||||||
7:0 | rdopcode | Read Opcode to use when not in XIP mode
|
RW | 0x3 |