indaddrtrig

         
      
Module Instance Base Address Register Address
i_qspi_qspiregs 0xFF809000 0xFF80901C

Offset: 0x1C

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

addr

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

addr

RW 0x0

indaddrtrig Fields

Bit Name Description Access Reset
31:0 addr
This register is used by the QSPI controller to determine whether incoming memory accesses on the QSPI AHB memory window are meant to access the SRAM FIFO or to be interpreted as direct access requests. When the incoming access is between indaddrtrig and indaddrtrig+15, the access is directed towards SRAM FIFO; otherwise it is interpreted as a direct access request. Note that it does not matter which address in the indaddrtrig to indaddrtrig+15 interval is accessed, any access is treated the same and will be directed to SRAM FIFO. When direct mode is not used, the recommended procedure is to leave indaddrtrig as 0, and use the base of the AHB memory window to access the SRAM FIFO.
RW 0x0