irqmask
0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_qspi_qspiregs | 0xFF809000 | 0xFF809044 |
Offset: 0x44
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
irq_mask_resv_fld RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
irq_mask_resv_fld RO 0x0 |
indsramfull RW 0x0 |
rxfull RW 0x0 |
rxthreshcmp RW 0x0 |
txfull RW 0x0 |
txthreshcmp RW 0x0 |
rxover RW 0x0 |
indxfrlvl RW 0x0 |
illegalacc RW 0x0 |
protwrattempt RW 0x0 |
indrdreject RW 0x0 |
indopdone RW 0x0 |
underflowdet RW 0x0 |
mode_m_fail_mask_fld RW 0x0 |
||
irqmask Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:13 | irq_mask_resv_fld | RO | 0x0 | |||||||
| 12 | indsramfull |
|
RW | 0x0 | ||||||
| 11 | rxfull |
|
RW | 0x0 | ||||||
| 10 | rxthreshcmp |
|
RW | 0x0 | ||||||
| 9 | txfull |
|
RW | 0x0 | ||||||
| 8 | txthreshcmp |
|
RW | 0x0 | ||||||
| 7 | rxover |
|
RW | 0x0 | ||||||
| 6 | indxfrlvl |
|
RW | 0x0 | ||||||
| 5 | illegalacc |
|
RW | 0x0 | ||||||
| 4 | protwrattempt |
|
RW | 0x0 | ||||||
| 3 | indrdreject |
|
RW | 0x0 | ||||||
| 2 | indopdone |
|
RW | 0x0 | ||||||
| 1 | underflowdet |
|
RW | 0x0 | ||||||
| 0 | mode_m_fail_mask_fld | RW | 0x0 |