emac Address Map

Module Instance Base Address End Address
i_emac_emac0 0xFF800000 0xFF801FFF
i_emac_emac1 0xFF802000 0xFF803FFF
i_emac_emac2 0xFF804000 0xFF807FFF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
gmacgrp_mac_configuration 0x0 32 RW 0x0 
 Register 0 (MAC Configuration Register)  

The MAC Configuration register establishes receive and transmit operating modes.
gmacgrp_mac_frame_filter 0x4 32 RW 0x0 
 Register 1 (MAC Frame Filter) 

The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames.
gmacgrp_gmii_address 0x10 32 RW 0x0 
 Register 4 (GMII Address Register)  

The GMII Address register controls the management cycles to the external PHY through the management interface.

Note: This register is present for all PHY interface when you select the Station Management (MDIO) feature in coreConsultant.
gmacgrp_gmii_data 0x14 32 RW 0x0 
 Register 5 (GMII Data Register) 

The GMII Data register stores Write data to be written to the PHY register located at the address specified in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register located at the address specified by Register 4.
gmacgrp_flow_control 0x18 32 RW 0x0 
 Register 6 (Flow Control Register)   

The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC's Flow control module. A Write to a register with the Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register.
gmacgrp_vlan_tag 0x1C 32 RW 0x0 
 Register 7 (VLAN Tag Register)   

The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with 16'h8100, and the following two bytes are compared with the VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive frame status. The legal length of the frame is increased from 1,518 bytes to 1,522 bytes.
If the VLAN Tag register is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to these register should be performed only after at least four clock cycles in the destination clock domain.
gmacgrp_version 0x20 32 RO 0x1037 
 Register 8 (Version Register)   

The Version registers identifies the version of the DWC_gmac.
gmacgrp_debug 0x24 32 RO 0x0 
 Register 9 (Debug Register)   

The Debug register gives the status of all main modules of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data-paths.

Note:  

The reset values, given for the Debug register, are valid only if the  following clocks are present during the reset operation:  
 * clk_csr_i, clk_app_i, hclk_i, or aclk_i  
 * clk_tx_i 
 * clk_rx_i
gmacgrp_lpi_control_status 0x30 32 RW 0x0 
 Register 12 (LPI Control and Status Register)   

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
gmacgrp_lpi_timers_control 0x34 32 RW 0x3E80000 
 Register 13 (LPI Timers Control Register)   

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.
gmacgrp_interrupt_status 0x38 32 RO 0x0 
 Register 14 (Interrupt Register)   

The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt events are generated only when the corresponding feature is enabled during operation. Therefore, these bits are reserved when the corresponding features are not present in the core.
gmacgrp_interrupt_mask 0x3C 32 RW 0x0 
 Register 15 (Interrupt Mask Register)  

The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register.
gmacgrp_mac_address0_high 0x40 32 RW 0x8000FFFF 
 Register 16 (MAC Address0 High Register)   

The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address0_low 0x44 32 RW 0xFFFFFFFF 
 Register 17 (MAC Address0 Low Register)   

The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC address of the station.
gmacgrp_mac_address1_high 0x48 32 RW 0xFFFF 
 Register 18 (MAC Address1 High Register)  

The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address1_low 0x4C 32 RW 0xFFFFFFFF 
 Register 19 (MAC Address1 Low Register)   

The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station.
gmacgrp_mac_address2_high 0x50 32 RW 0xFFFF 
 Register 20 (MAC Address2 High Register)   

The MAC Address2 High register holds the upper 16 bits of the third 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address2 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address2 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address2_low 0x54 32 RW 0xFFFFFFFF 
 Register 21 (MAC Address2 Low Register)   

The MAC Address2 Low register holds the lower 32 bits of the third 6-byte MAC address of the station.
gmacgrp_mac_address3_high 0x58 32 RW 0xFFFF 
 Register 22 (MAC Address3 High Register)   

The MAC Address3 High register holds the upper 16 bits of the fourth 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address3 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address3 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address3_low 0x5C 32 RW 0xFFFFFFFF 
 Register 23 (MAC Address3 Low Register)   

The MAC Address3 Low register holds the lower 32 bits of the fourth 6-byte MAC address of the station.
gmacgrp_mac_address4_high 0x60 32 RW 0xFFFF 
 Register 24 (MAC Address4 High Register)   

The MAC Address4 High register holds the upper 16 bits of the fifth 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address4 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address4 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address4_low 0x64 32 RW 0xFFFFFFFF 
 Register 25 (MAC Address4 Low Register)   

The MAC Address4 Low register holds the lower 32 bits of the fifth 6-byte MAC address of the station.
gmacgrp_mac_address5_high 0x68 32 RW 0xFFFF 
 Register 26 (MAC Address5 High Register) 

The MAC Address5 High register holds the upper 16 bits of the sixth 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address5 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address5 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address5_low 0x6C 32 RW 0xFFFFFFFF 
 Register 27 (MAC Address5 Low Register)   

The MAC Address5 Low register holds the lower 32 bits of the sixth 6-byte MAC address of the station.
gmacgrp_mac_address6_high 0x70 32 RW 0xFFFF 
 Register 28 (MAC Address6 High Register)   

The MAC Address6 High register holds the upper 16 bits of the seventh 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address6 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address6 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address6_low 0x74 32 RW 0xFFFFFFFF 
 Register 29 (MAC Address6 Low Register)   

The MAC Address6 Low register holds the lower 32 bits of the seventh 6-byte MAC address of the station.
gmacgrp_mac_address7_high 0x78 32 RW 0xFFFF 
 Register 30 (MAC Address7 High Register)   

The MAC Address7 High register holds the upper 16 bits of the eighth 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address7 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address7 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address7_low 0x7C 32 RW 0xFFFFFFFF 
 Register 31 (MAC Address7 Low Register)   

The MAC Address7 Low register holds the lower 32 bits of the eighth 6-byte MAC address of the station.
gmacgrp_mac_address8_high 0x80 32 RW 0xFFFF 
 Register 32 (MAC Address8 High Register)   

The MAC Address8 High register holds the upper 16 bits of the nineth 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address8 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address8 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address8_low 0x84 32 RW 0xFFFFFFFF 
 Register 33 (MAC Address8 Low Register)   

The MAC Address8 Low register holds the lower 32 bits of the nineth 6-byte MAC address of the station.
gmacgrp_mac_address9_high 0x88 32 RW 0xFFFF 
 Register 34 (MAC Address9 High Register)   

The MAC Address9 High register holds the upper 16 bits of the tenth 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address9 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address9 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address9_low 0x8C 32 RW 0xFFFFFFFF 
 Register 35 (MAC Address9 Low Register)   

The MAC Address9 Low register holds the lower 32 bits of the tenth 6-byte MAC address of the station.
gmacgrp_mac_address10_high 0x90 32 RW 0xFFFF 
 Register 36 (MAC Address10 High Register)   

The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address10 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address10 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address10_low 0x94 32 RW 0xFFFFFFFF 
 Register 37 (MAC Address10 Low Register)   

The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC address of the station.
gmacgrp_mac_address11_high 0x98 32 RW 0xFFFF 
 Register 38 (MAC Address11 High Register)   

The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address11 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address11 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address11_low 0x9C 32 RW 0xFFFFFFFF 
 Register 39 (MAC Address1 Low Register)   

The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC address of the station.
gmacgrp_mac_address12_high 0xA0 32 RW 0xFFFF 
 Register 40 (MAC Address12 High Register ) 

The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address13 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address12 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address12_low 0xA4 32 RW 0xFFFFFFFF 
 Register 41 (MAC Address12 Low Register)   

The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC address of the station.
gmacgrp_mac_address13_high 0xA8 32 RW 0xFFFF 
 Register 42 (MAC Address13 High Register)   

The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address13 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address13 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address13_low 0xAC 32 RW 0xFFFFFFFF 
 Register 43 (MAC Address13 Low Register)   

The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC address of the station.
gmacgrp_mac_address14_high 0xB0 32 RW 0xFFFF 
 Register 44 (MAC Address14 High Register)   

The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address15 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address14 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address14_low 0xB4 32 RW 0xFFFFFFFF 
 Register 45 (MAC Address14 Low Register)   

The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station.
gmacgrp_mac_address15_high 0xB8 32 RW 0xFFFF 
 Register 46 (MAC Address15 High Register)  

The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC address of the station.
If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address15 Low Register are written. For proper synchronization updates, the consecutive writes to this MAC Address15 Low Register should be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address15_low 0xBC 32 RW 0xFFFFFFFF 
 Register 47 (MAC Address15 Low Register)   

The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station.
gmacgrp_sgmii_rgmii_smii_control_status 0xD8 32 RO 0x0 
Register 54 (SGMII/RGMII/SMII Status Register)
gmacgrp_wdog_timeout 0xDC 32 RW 0x0 
 Register 55 (Watchdog Timeout Register) 
              This register controls the watchdog timeout for received frames.
gmacgrp_genpio 0xE0 32 RW 0x0 
 Register 56 (General Purpose IO Register) 
              This register provides the control to drive up to 4 bits of output ports (GPO) and the status of up to 4 input
              ports (GPIS). It also provides the control to generate interrupts on events occurring on the gpi_i pin.
gmacgrp_mmc_control 0x100 32 RW 0x0 
 Register 64 (MMC Control Register) 

The MMC Control register establishes the operating mode of the management counters.

Note:
The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set both bits in the same write cycle, all counters are cleared and the bit 4 is not set.
gmacgrp_mmc_receive_interrupt 0x104 32 RO 0x0 
 Register 65 (MMC Receive Interrupt Register) 

The MMC Receive Interrupt register maintains the interrupts that are generated when the following happens:
 * Receive statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter).
 * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). 
When the Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
gmacgrp_mmc_transmit_interrupt 0x108 32 RO 0x0 
 Register 66 (MMC Transmit Interrupt Register) 

The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
gmacgrp_mmc_receive_interrupt_mask 0x10C 32 RW 0x0 
Regsiter 67 (MMC Receive Interrupt Mask Register)

The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide.
gmacgrp_mmc_transmit_interrupt_mask 0x110 32 RW 0x0 
 Register 68 (MMC Transmit Interrupt Mask Register) 

The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide.
gmacgrp_txoctetcount_gb 0x114 32 RO 0x0 
 Register 69 (Transmit Octet Count for Good and Bad Frames) 

This register maintains the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes.
gmacgrp_txframecount_gb 0x118 32 RO 0x0 
 Register 70 (Transmit Frame Count for Good and Bad Frames) 

This register maintains the number of good and bad frames transmitted, exclusive of retried frames.
gmacgrp_txbroadcastframes_g 0x11C 32 RO 0x0 
 Register 71 (Transmit Frame Count for Good Broadcast Frames) 

This register maintains the number of transmitted good broadcast frames.
gmacgrp_txmulticastframes_g 0x120 32 RO 0x0 
 Register 72 (Transmit Frame Count for Good Multicast Frames) 

This register maintains the number of transmitted good multicast frames.
gmacgrp_tx64octets_gb 0x124 32 RO 0x0 
 Register 73 (Transmit Octet Count for Good and Bad 64 Byte Frames) 

This register maintains the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames.
gmacgrp_tx65to127octets_gb 0x128 32 RO 0x0 
 Register 74 (Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames) 

This register maintains the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames.
gmacgrp_tx128to255octets_gb 0x12C 32 RO 0x0 
 Register 75 (Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames) 

This register maintains the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames.
gmacgrp_tx256to511octets_gb 0x130 32 RO 0x0 
 Register 76 (Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames) 

This register maintains the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames.
gmacgrp_tx512to1023octets_gb 0x134 32 RO 0x0 
 Register 77 (Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames) 

This register maintains the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames.
gmacgrp_tx1024tomaxoctets_gb 0x138 32 RO 0x0 
 Register 78 (Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames) 

This register maintains the number of transmitted good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames.
gmacgrp_txunicastframes_gb 0x13C 32 RO 0x0 
 Register 79 (Transmit Frame Count for Good and Bad Unicast Frames) 

This register maintains the number of transmitted good and bad unicast frames.
gmacgrp_txmulticastframes_gb 0x140 32 RO 0x0 
 Register 80 (Transmit Frame Count for Good and Bad Multicast Frames) 

This register maintains the number of transmitted good and bad multicast frames.
gmacgrp_txbroadcastframes_gb 0x144 32 RO 0x0 
 Register 81 (Transmit Frame Count for Good and Bad Broadcast Frames) 

This register maintains the number of transmitted good and bad broadcast frames.
gmacgrp_txunderflowerror 0x148 32 RO 0x0 
 Register 82 (Transmit Frame Count for Underflow Error Frames) 

This register maintains the number of frames aborted because of frame underflow error.
gmacgrp_txsinglecol_g 0x14C 32 RO 0x0 
 Register 83 (Transmit Frame Count for Frames Transmitted after Single Collision) 

This register maintains the number of successfully transmitted frames after a single collision in the half-duplex mode.
gmacgrp_txmulticol_g 0x150 32 RO 0x0 
 Register 84 (Transmit Frame Count for Frames Transmitted after Multiple Collision) 

This register maintains the number of successfully transmitted frames after multiple collisions in the half-duplex mode.
gmacgrp_txdeferred 0x154 32 RO 0x0 
 Register 85 (Transmit Frame Count for Deferred Frames) 

This register maintains the number of successfully transmitted frames after a deferral in the half-duplex mode.
gmacgrp_txlatecol 0x158 32 RO 0x0 
 Register 86 (Transmit Frame Count for Late Collision Error Frames) 

This register maintains the number of frames aborted because of late collision error.
gmacgrp_txexesscol 0x15C 32 RO 0x0 
 Register 87 (Transmit Frame Count for Excessive Collision Error Frames) 

This register maintains the number of frames aborted because of excessive (16) collision error.
gmacgrp_txcarriererr 0x160 32 RO 0x0 
 Register 88 (Transmit Frame Count for Carrier Sense Error Frames) 

This register maintains the number of frames aborted because of carrier sense error (no carrier or loss of carrier).
gmacgrp_txoctetcnt 0x164 32 RO 0x0 
 Register 89 (Transmit Octet Count for Good Frames) 

This register maintains the number of bytes transmitted, exclusive of preamble, in good frames.
gmacgrp_txframecount_g 0x168 32 RO 0x0 
 Register 90 (Transmit Frame Count for Good Frames) 

This register maintains the number of transmitted good frames, exclusive of preamble.
gmacgrp_txexcessdef 0x16C 32 RO 0x0 
 Register 91 (Transmit Frame Count for Excessive Deferral Error Frames) 

This register maintains the number of frames aborted because of  excessive deferral error, that is, frames deferred for more than two max-sized frame times.
gmacgrp_txpauseframes 0x170 32 RO 0x0 
 Register 92 (Transmit Frame Count for Good PAUSE Frames) 

This register maintains the number of transmitted good PAUSE frames.
gmacgrp_txvlanframes_g 0x174 32 RO 0x0 
 Register 93 (Transmit Frame Count for Good VLAN Frames) 

This register maintains the number of transmitted good VLAN frames, exclusive of retried frames.
gmacgrp_txoversize_g 0x178 32 RO 0x0 
 Register 94 (Transmit Frame Count for Good Oversize Frames) 

This register maintains the number of transmitted good Oversize frames, exclusive of retried frames.
gmacgrp_rxframecount_gb 0x180 32 RO 0x0 
 Register 96 (Receive Frame Count for Good and Bad Frames) 

This register maintains the number of received good and bad frames.
gmacgrp_rxoctetcount_gb 0x184 32 RO 0x0 
 Register 97 (Receive Octet Count for Good and Bad Frames) 

This register maintains the number of bytes received, exclusive of preamble, in good and bad frames.
gmacgrp_rxoctetcount_g 0x188 32 RO 0x0 
 Register 98 (Receive Octet Count for Good Frames)  

This register maintains the number of bytes received, exclusive of preamble, only in good frames.
gmacgrp_rxbroadcastframes_g 0x18C 32 RO 0x0 
 Register 99 (Receive Frame Count for Good Broadcast Frames)  

This register maintains the number of received good broadcast frames.
gmacgrp_rxmulticastframes_g 0x190 32 RO 0x0 
 Register 100 (Receive Frame Count for Good Multicast Frames)  

This register maintains the number of received good multicast frames.
gmacgrp_rxcrcerror 0x194 32 RO 0x0 
 Register 101 (Receive Frame Count for CRC Error Frames) 

This register maintains the number of frames received with CRC error.
gmacgrp_rxalignmenterror 0x198 32 RO 0x0 
 Register 102 (Receive Frame Count for Alignment Error Frames) 

This register maintains the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode.
gmacgrp_rxrunterror 0x19C 32 RO 0x0 
 Register 103 (Receive Frame Count for Runt Error Frames) 

This register maintains the number of frames received with runt error(<64 bytes and CRC error).
gmacgrp_rxjabbererror 0x1A0 32 RO 0x0 
 Register 104 (Receive Frame Count for Jabber Error Frames) 

This register maintains the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames.
gmacgrp_rxundersize_g 0x1A4 32 RO 0x0 
 Register 105 (Receive Frame Count for Undersize Frames) 

This register maintains the number of frames received with length less than 64 bytes and without errors.
gmacgrp_rxoversize_g 0x1A8 32 RO 0x0 
 Register 106 (Receive Frame Count for Oversize Frames) 

This register maintains the number of frames received with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames) and without errors.
gmacgrp_rx64octets_gb 0x1AC 32 RO 0x0 
 Register 107 (Receive Frame Count for Good and Bad 64 Byte Frames) 

This register maintains the number of received good and bad frames with length 64 bytes, exclusive of preamble.
gmacgrp_rx65to127octets_gb 0x1B0 32 RO 0x0 
 Register 108 (Receive Frame Count for Good and Bad 65 to 127 Bytes Frames) 

This register maintains the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble.
gmacgrp_rx128to255octets_gb 0x1B4 32 RO 0x0 
 Register 109 (Receive Frame Count for Good and Bad 128 to 255 Bytes Frames) 

This register maintains the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble.
gmacgrp_rx256to511octets_gb 0x1B8 32 RO 0x0 
 Register 110 (Receive Frame Count for Good and Bad 256 to 511 Bytes Frames) 

This register maintains the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble.
gmacgrp_rx512to1023octets_gb 0x1BC 32 RO 0x0 
 Register 111 (Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames) 

This register maintains the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble.
gmacgrp_rx1024tomaxoctets_gb 0x1C0 32 RO 0x0 
 Register 112 (Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames) 

This register maintains the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble.
gmacgrp_rxunicastframes_g 0x1C4 32 RO 0x0 
 Register 113 (Receive Frame Count for Good Unicast Frames)  

This register maintains the number of received good unicast frames.
gmacgrp_rxlengtherror 0x1C8 32 RO 0x0 
 Register 114 (Receive Frame Count for Length Error Frames)  

This register maintains the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field.
gmacgrp_rxoutofrangetype 0x1CC 32 RO 0x0 
 Register 115 (Receive Frame Count for Out of Range Frames)  

This register maintains the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536).
gmacgrp_rxpauseframes 0x1D0 32 RO 0x0 
 Register 116 (Receive Frame Count for PAUSE Frames)  

This register maintains the number of received good and valid PAUSE frames.
gmacgrp_rxfifooverflow 0x1D4 32 RO 0x0 
 Register 117 (Receive Frame Count for FIFO Overflow Frames) 

This register maintains the number of received frames missed because of FIFO overflow.
gmacgrp_rxvlanframes_gb 0x1D8 32 RO 0x0 
 Register 118 (Receive Frame Count for Good and Bad VLAN Frames) 

This register maintains the number of received good and bad VLAN frames.
gmacgrp_rxwatchdogerror 0x1DC 32 RO 0x0 
 Register 119 (Receive Frame Count for Watchdog Error Frames) 

This register maintains the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes or value programmed in Register 55 (Watchdog Timeout Register)).
gmacgrp_rxrcverror 0x1E0 32 RO 0x0 
 Register 120 (Receive Frame Count for Receive Error Frames) 
This register maintains the number of frames received with error because of the GMII/MII RXER error.
gmacgrp_rxctrlframes_g 0x1E4 32 RO 0x0 
 Register 121 (Receive Frame Count for Good Control Frames Frames) 

This register maintains the number of good control frames received.
gmacgrp_mmc_ipc_receive_interrupt_mask 0x200 32 RW 0x0 
Register 128 (MMC Receive Checksum Offload Interrupt Mask Register)
gmacgrp_mmc_ipc_receive_interrupt 0x208 32 RO 0x0 
Register 130 (MMC Receive Checksum Offload Interrupt Register)
gmacgrp_rxipv4_gd_frms 0x210 32 RO 0x0 
Register 132 (rxipv4_gd_frms Register)
gmacgrp_rxipv4_hdrerr_frms 0x214 32 RO 0x0 
Register 133 (rxipv4_hdrerr_frms Register)
gmacgrp_rxipv4_nopay_frms 0x218 32 RO 0x0 
Register 134 (rxipv4_nopay_frms Register)
gmacgrp_rxipv4_frag_frms 0x21C 32 RO 0x0 
Register 135 (rxipv4_frag_frms Register)
gmacgrp_rxipv4_udsbl_frms 0x220 32 RO 0x0 
Register 136 (rxipv4_udsbl_frms Register)
gmacgrp_rxipv6_gd_frms 0x224 32 RO 0x0 
Register 137 (rxipv6_gd_frms Register)
gmacgrp_rxipv6_hdrerr_frms 0x228 32 RO 0x0 
Register 138 (rxipv6_hdrerr_frms Register)
gmacgrp_rxipv6_nopay_frms 0x22C 32 RO 0x0 
Register 139 (rxipv6_nopay_frms)
gmacgrp_rxudp_gd_frms 0x230 32 RO 0x0 
Register 140 (rxudp_gd_frms Register)
gmacgrp_rxudp_err_frms 0x234 32 RO 0x0 
Register 141 (rxudp_err_frms Register)
gmacgrp_rxtcp_gd_frms 0x238 32 RO 0x0 
Register 142 (rxtcp_gd_frms Register)
gmacgrp_rxtcp_err_frms 0x23C 32 RO 0x0 
Register 143 (rxtcp_err_frms Register)
gmacgrp_rxicmp_gd_frms 0x240 32 RO 0x0 
Register 144 (rxicmp_gd_frms Register)
gmacgrp_rxicmp_err_frms 0x244 32 RO 0x0 
Register 145 (rxicmp_err_frms Register)
gmacgrp_rxipv4_gd_octets 0x250 32 RO 0x0 
Register 148 (rxipv4_gd_octets Register)
gmacgrp_rxipv4_hdrerr_octets 0x254 32 RO 0x0 
Register 149 (rxipv4_hdrerr_octets)
gmacgrp_rxipv4_nopay_octets 0x258 32 RO 0x0 
Register 150 (rxipv4_nopay_octets Register)
gmacgrp_rxipv4_frag_octets 0x25C 32 RO 0x0 
Register 151 (rxipv4_frag_octets Register)
gmacgrp_rxipv4_udsbl_octets 0x260 32 RO 0x0 
Register 152 (rxipv4_udsbl_octets Register)
gmacgrp_rxipv6_gd_octets 0x264 32 RO 0x0 
Register 153 (rxipv6_gd_octets Register)
gmacgrp_rxipv6_hdrerr_octets 0x268 32 RO 0x0 
Register 154 (rxipv6_hdrerr_octets Register)
gmacgrp_rxipv6_nopay_octets 0x26C 32 RO 0x0 
Register 155 (rxipv6_nopay_octets Register)
gmacgrp_rxudp_gd_octets 0x270 32 RO 0x0 
Register 156 (rxudp_gd_octets Register)
gmacgrp_rxudp_err_octets 0x274 32 RO 0x0 
Register 157 (rxudp_err_octets Register)
gmacgrp_rxtcp_gd_octets 0x278 32 RO 0x0 
Register 158 (rxtcp_gd_octets Register)
gmacgrp_rxtcperroctets 0x27C 32 RO 0x0 
Register 159 (rxtcp_err_octets Register)
gmacgrp_rxicmp_gd_octets 0x280 32 RO 0x0 
Register 160 (rxicmp_gd_octets Register)
gmacgrp_rxicmp_err_octets 0x284 32 RO 0x0 
Register 161 (rxicmp_err_octets Register)
gmacgrp_l3_l4_control0 0x400 32 RW 0x0 
 Register 256 (Layer 3 and Layer 4 Control Register 0) 

This register controls the operations of the filter 0 of Layer 3 and Layer 4.
gmacgrp_layer4_address0 0x404 32 RW 0x0 
 Register 257 (Layer 4 Address Register 0) 


You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option in coreConsultant. If the Layer 3 and Layer 4 Address Registers are configured to be double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
gmacgrp_layer3_addr0_reg0 0x410 32 RW 0x0 
 Register 260 (Layer 3 Address 0 Register 0) 

For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
gmacgrp_layer3_addr1_reg0 0x414 32 RW 0x0 
 Register 261 (Layer 3 Address 1 Register 0) 

For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP Destination Address field. For IPv6 frames, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
gmacgrp_layer3_addr2_reg0 0x418 32 RW 0x0 
 Register 262 (Layer 3 Address 2 Register 0) 

For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.
gmacgrp_layer3_addr3_reg0 0x41C 32 RW 0x0 
 Register 263 (Layer 3 Address 3 Register 0) 

For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames, it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field.
gmacgrp_l3_l4_control1 0x430 32 RW 0x0 
Register 268 (Layer 3 and Layer 4 Control Register 1)
gmacgrp_layer4_address1 0x434 32 RW 0x0 
Register 269 (Layer 4 Address Register 1)
gmacgrp_layer3_addr0_reg1 0x440 32 RW 0x0 
Register 272 (Layer 3 Address 0 Register 1)
gmacgrp_layer3_addr1_reg1 0x444 32 RW 0x0 
Register 273 (Layer 3 Address 1 Register 1)
gmacgrp_layer3_addr2_reg1 0x448 32 RW 0x0 
Register 274 (Layer 3 Address 2 Register 1)
gmacgrp_layer3_addr3_reg1 0x44C 32 RW 0x0 
Register 275 (Layer 3 Address 3 Register 1)
gmacgrp_l3_l4_control2 0x460 32 RW 0x0 
Register 280 (Layer 3 and Layer 4 Control Register 2)
gmacgrp_layer4_address2 0x464 32 RW 0x0 
Register 281 (Layer 4 Address Register 2)
gmacgrp_layer3_addr0_reg2 0x470 32 RW 0x0 
Register 284 (Layer 3 Address 0 Register 2)
gmacgrp_layer3_addr1_reg2 0x474 32 RW 0x0 
Register 285 (Layer 3 Address 1 Register 2)
gmacgrp_layer3_addr2_reg2 0x478 32 RW 0x0 
Register 286 (Layer 3 Address 2 Register 2)
gmacgrp_layer3_addr3_reg2 0x47C 32 RW 0x0 
Register 287 (Layer 3 Address 3 Register 2)
gmacgrp_l3_l4_control3 0x490 32 RW 0x0 
Register 292 (Layer 3 and Layer 4 Control Register 3)
gmacgrp_layer4_address3 0x494 32 RW 0x0 
Register 293 (Layer 4 Address Register 3)
gmacgrp_layer3_addr0_reg3 0x4A0 32 RW 0x0 
Register 296 (Layer 3 Address 0 Register 3)
gmacgrp_layer3_addr1_reg3 0x4A4 32 RW 0x0 
Register 297 (Layer 3 Address 1 Register 3)
gmacgrp_layer3_addr2_reg3 0x4A8 32 RW 0x0 
Register 298 (Layer 3 Address 2 Register 3)
gmacgrp_layer3_addr3_reg3 0x4AC 32 RW 0x0 
Register 299 (Layer 3 Address 3 Register 3)
gmacgrp_hash_table_reg0 0x500 32 RW 0x0 
Register 320 (Hash Table Register 0)
gmacgrp_hash_table_reg1 0x504 32 RW 0x0 
Register 321 (Hash Table Register 1)
gmacgrp_hash_table_reg2 0x508 32 RW 0x0 
Register 322 (Hash Table Register 2)
gmacgrp_hash_table_reg3 0x50C 32 RW 0x0 
Register 323 (Hash Table Register 3)
gmacgrp_hash_table_reg4 0x510 32 RW 0x0 
Register 324 (Hash Table Register 4)
gmacgrp_hash_table_reg5 0x514 32 RW 0x0 
Register 325 (Hash Table Register 5)
gmacgrp_hash_table_reg6 0x518 32 RW 0x0 
Register 326 (Hash Table Register 6)
gmacgrp_hash_table_reg7 0x51C 32 RW 0x0 
Register 327 (Hash Table Register 7)
gmacgrp_vlan_incl_reg 0x584 32 RW 0x0 
 Register 353 (VLAN Tag Inclusion or Replacement Register)  

The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the transmit frames.
gmacgrp_vlan_hash_table_reg 0x588 32 RW 0x0 
Register 354 (VLAN Hash Table Register)
gmacgrp_timestamp_control 0x700 32 RW 0x2000 
 Register 448 (Timestamp Control Register) 

This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.

Note: 
 * Bits[5:1] are reserved when External Timestamp Input feature is enabled. 
 * Bits[19:8] are reserved and read-only when Advanced Timestamp feature is not enabled.
 * Bits[28:24] are reserved and read-only when Auxiliary Snapshot feature is not enabled.
 * Release 3.60a onwards, the functions of Bits 17 and 16 (SNAPTYPSEL) have changed. These functions are not backward compatible with the functions described in release 3.50a.
gmacgrp_sub_second_increment 0x704 32 RW 0x0 
Register 449 (Sub-Second Increment Register)
gmacgrp_system_time_seconds 0x708 32 RO 0x0 
Register 450 (System Time - Seconds Register)
gmacgrp_system_time_nanoseconds 0x70C 32 RO 0x0 
Register 451 (System Time - Nanoseconds Register)
gmacgrp_system_time_seconds_update 0x710 32 RW 0x0 
Register 452 (System Time - Seconds Update Register)
gmacgrp_system_time_nanoseconds_update 0x714 32 RW 0x0 
Register 453 (System Time - Nanoseconds Update Register)
gmacgrp_timestamp_addend 0x718 32 RW 0x0 
Register 454 (Timestamp Addend Register)
gmacgrp_target_time_seconds 0x71C 32 RW 0x0 
Register 455 (Target Time Seconds Register)
gmacgrp_target_time_nanoseconds 0x720 32 RW 0x0 
Register 456 (Target Time Nanoseconds Register)
gmacgrp_system_time_higher_word_seconds 0x724 32 RW 0x0 
Register 457 (System Time - Higher Word Seconds Register)
gmacgrp_timestamp_status 0x728 32 RO 0x0 
Register 458 (Timestamp Status Register)
gmacgrp_pps_control 0x72C 32 RW 0x0 
Register 459 (PPS Control Register)
gmacgrp_auxiliary_timestamp_nanoseconds 0x730 32 RO 0x0 
Register 460 (Auxiliary Timestamp - Nanoseconds Register)
gmacgrp_auxiliary_timestamp_seconds 0x734 32 RO 0x0 
Register 461 (Auxiliary Timestamp - Seconds Register)
gmacgrp_pps0_interval 0x760 32 RW 0x0 
Register 472 (PPS0 Interval Register)
gmacgrp_pps0_width 0x764 32 RW 0x0 
Register 473 (PPS0 Width Register)
gmacgrp_mac_address16_high 0x800 32 RW 0xFFFF 
 Register 512 (MAC Address16 High Register)   

The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address16 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address16 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address16_low 0x804 32 RW 0xFFFFFFFF 
 Register 513 (MAC Address16 Low Register)   

The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station.
gmacgrp_mac_address17_high 0x808 32 RW 0xFFFF 
 Register 514 (MAC Address17 High Register)   

The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address17 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address17 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address17_low 0x80C 32 RW 0xFFFFFFFF 
 Register 515 (MAC Address17 Low Register)   

The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station.
gmacgrp_mac_address18_high 0x810 32 RW 0xFFFF 
 Register 516 (MAC Address18 High Register)   

The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address18 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address18 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address18_low 0x814 32 RW 0xFFFFFFFF 
 Register 517 (MAC Address18 Low Register)   

The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC address of the station.
gmacgrp_mac_address19_high 0x818 32 RW 0xFFFF 
 Register 518 (MAC Address19 High Register)   

The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address19 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address19 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address19_low 0x81C 32 RW 0xFFFFFFFF 
 Register 519 (MAC Address19 Low Register)   

The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC address of the station.
gmacgrp_mac_address20_high 0x820 32 RW 0xFFFF 
 Register 520 (MAC Address20 High Register)   

The MAC Address20 High register holds the upper 16 bits of the 21st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address20 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address20 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address20_low 0x824 32 RW 0xFFFFFFFF 
 Register 521 (MAC Address20 Low Register)   

The MAC Address20 Low register holds the lower 32 bits of the 21st 6-byte MAC address of the station.
gmacgrp_mac_address21_high 0x828 32 RW 0xFFFF 
 Register 522 (MAC Address21 High Register)   

The MAC Address21 High register holds the upper 16 bits of the 22nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address21 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address21 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address21_low 0x82C 32 RW 0xFFFFFFFF 
 Register 523 (MAC Address21 Low Register)   

The MAC Address21 Low register holds the lower 32 bits of the 22nd 6-byte MAC address of the station.
gmacgrp_mac_address22_high 0x830 32 RW 0xFFFF 
 Register 524 (MAC Address22 High Register)   

The MAC Address22 High register holds the upper 16 bits of the 23rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address22 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address22 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address22_low 0x834 32 RW 0xFFFFFFFF 
 Register 525 (MAC Address22 Low Register)   

The MAC Address22 Low register holds the lower 32 bits of the 23rd 6-byte MAC address of the station.
gmacgrp_mac_address23_high 0x838 32 RW 0xFFFF 
 Register 526 (MAC Address23 High Register   

The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address23 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address23 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address23_low 0x83C 32 RW 0xFFFFFFFF 
 Register 527 (MAC Address23 Low Register)  

The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC address of the station.
gmacgrp_mac_address24_high 0x840 32 RW 0xFFFF 
 Register 528 (MAC Address24 High Register)   

The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address24 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address24 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address24_low 0x844 32 RW 0xFFFFFFFF 
 Register 529 (MAC Address24 Low Register)   

The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC address of the station.
gmacgrp_mac_address25_high 0x848 32 RW 0xFFFF 
 Register 530 (MAC Address25 High Register)   

The MAC Address25 High register holds the upper 16 bits of the 6-byte 26th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address25 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address25 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address25_low 0x84C 32 RW 0xFFFFFFFF 
 Register 531 (MAC Address25 Low Register)   

The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC address of the station.
gmacgrp_mac_address26_high 0x850 32 RW 0xFFFF 
 Register 532 (MAC Address26 High Register)   

The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address26 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address26 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address26_low 0x854 32 RW 0xFFFFFFFF 
 Register 533 (MAC Address26 Low Register) 

The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC address of the station.
gmacgrp_mac_address27_high 0x858 32 RW 0xFFFF 
 Register 534 (MAC Address27 High Register)   

The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address27 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address27 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address27_low 0x85C 32 RW 0xFFFFFFFF 
 Register 535 (MAC Address27 Low Register)   

The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC address of the station.
gmacgrp_mac_address28_high 0x860 32 RW 0xFFFF 
 Register 536 (MAC Address28 High Register)   

The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address28 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address28 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address28_low 0x864 32 RW 0xFFFFFFFF 
 Register 537 (MAC Address28 Low Register)   

The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC address of the station.
gmacgrp_mac_address29_high 0x868 32 RW 0xFFFF 
 Register 538 (MAC Address29 High Register)   

The MAC Address29 High register holds the upper 16 bits of the 6-byte 30th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address29 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address29 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address29_low 0x86C 32 RW 0xFFFFFFFF 
 Register 539 (MAC Address29 Low Register)   

The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC address of the station.
gmacgrp_mac_address30_high 0x870 32 RW 0xFFFF 
 Register 540 (MAC Address30 High Register)   

The MAC Address30 High register holds the upper 16 bits of the 31st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address30 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address30 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address30_low 0x874 32 RW 0xFFFFFFFF 
 Register 541 (MAC Address30 Low Register)   

The MAC Address30 Low register holds the lower 32 bits of the 31st 6-byte MAC address of the station.
gmacgrp_mac_address31_high 0x878 32 RW 0xFFFF 
 Register 542 (MAC Address31 High Register) 

The MAC Address31 High register holds the upper 16 bits of the 32nd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address31 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address31 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address31_low 0x87C 32 RW 0xFFFFFFFF 
 Register 543 (MAC Address31 Low Register)   

The MAC Address31 Low register holds the lower 32 bits of the 32nd 6-byte MAC address of the station.
gmacgrp_mac_address32_high 0x880 32 RW 0xFFFF 
 Register 544 (MAC Address32 High Register)   

The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address32 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address32 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address32_low 0x884 32 RW 0xFFFFFFFF 
 Register 545 (MAC Address32 Low Register)   

The MAC Address32 Low register holds the lower 32 bits of the 33rd 6-byte MAC address of the station.
gmacgrp_mac_address33_high 0x888 32 RW 0xFFFF 
 Register 546 (MAC Address33 High Register)   

The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address33 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address33 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address33_low 0x88C 32 RW 0xFFFFFFFF 
 Register 547 (MAC Address33 Low Register) 

The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC address of the station.
gmacgrp_mac_address34_high 0x890 32 RW 0xFFFF 
 Register 548 (MAC Address34 High Register)   

The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address34 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address34 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address34_low 0x894 32 RW 0xFFFFFFFF 
 Register 549 (MAC Address34 Low Register)   

The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC address of the station.
gmacgrp_mac_address35_high 0x898 32 RW 0xFFFF 
 Register 550 (MAC Address35 High Register)   

The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address35 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address35 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address35_low 0x89C 32 RW 0xFFFFFFFF 
 Register 551 (MAC Address35 Low Register)   

The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC address of the station.
gmacgrp_mac_address36_high 0x8A0 32 RW 0xFFFF 
 Register 552 (MAC Address36 High Register)   

The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address36 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address36 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address36_low 0x8A4 32 RW 0xFFFFFFFF 
 Register 553 (MAC Address36 Low Register)   

The MAC Address36 Low register holds the lower 32 bits of the 34th 6-byte MAC address of the station.
gmacgrp_mac_address37_high 0x8A8 32 RW 0xFFFF 
 Register 554 (MAC Address37 High Register)   

The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address37 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address37 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address37_low 0x8AC 32 RW 0xFFFFFFFF 
 Register 555 (MAC Address37 Low Register) 

The MAC Address37 Low register holds the lower 32 bits of the 37th 6-byte MAC address of the station.
gmacgrp_mac_address38_high 0x8B0 32 RW 0xFFFF 
 Register 556 (MAC Address38 High Register)   

The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address38 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address38 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address38_low 0x8B4 32 RW 0xFFFFFFFF 
 Register 557 (MAC Address38 Low Register)   

The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC address of the station.
gmacgrp_mac_address39_high 0x8B8 32 RW 0xFFFF 
 Register 558 (MAC Address39 High Register) 

The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address40 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address40 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address39_low 0x8BC 32 RW 0xFFFFFFFF 
 Register 559 (MAC Address39 Low Register)   

The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC address of the station.
gmacgrp_mac_address40_high 0x8C0 32 RW 0xFFFF 
 Register 560 (MAC Address40 High Register)   

The MAC Address40 High register holds the upper 16 bits of the 41st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address40 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address40 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address40_low 0x8C4 32 RW 0xFFFFFFFF 
 Register 561 (MAC Address40 Low Register)  

The MAC Address40 Low register holds the lower 32 bits of the 41st 6-byte MAC address of the station.
gmacgrp_mac_address41_high 0x8C8 32 RW 0xFFFF 
 Register 562 (MAC Address41 High Register)   

The MAC Address41 High register holds the upper 16 bits of the 42nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address41 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address41 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address41_low 0x8CC 32 RW 0xFFFFFFFF 
 Register 563 (MAC Address41 Low Register)   

The MAC Address41 Low register holds the lower 32 bits of the 42nd 6-byte MAC address of the station.
gmacgrp_mac_address42_high 0x8D0 32 RW 0xFFFF 
 Register 564 (MAC Address42 High Register)   

The MAC Address42 High register holds the upper 16 bits of the 43rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address42 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address42 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address42_low 0x8D4 32 RW 0xFFFFFFFF 
 Register 565 (MAC Address42 Low Register)  

The MAC Address42 Low register holds the lower 32 bits of the 43rd 6-byte MAC address of the station.
gmacgrp_mac_address43_high 0x8D8 32 RW 0xFFFF 
 Register 566 (MAC Address43 High Register)   

The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address43 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address43 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address43_low 0x8DC 32 RW 0xFFFFFFFF 
 Register 567 (MAC Address43 Low Register) 

The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC address of the station.
gmacgrp_mac_address44_high 0x8E0 32 RW 0xFFFF 
 Register 568 (MAC Address44 High Register)   

The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address44 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address44 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address44_low 0x8E4 32 RW 0xFFFFFFFF 
 Register 569 (MAC Address44 Low Register)  

The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC address of the station.
gmacgrp_mac_address45_high 0x8E8 32 RW 0xFFFF 
 Register 570 (MAC Address45 High Register)   

The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address45 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address45 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address45_low 0x8EC 32 RW 0xFFFFFFFF 
 Register 571 (MAC Address45 Low Register)   

The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC address of the station.
gmacgrp_mac_address46_high 0x8F0 32 RW 0xFFFF 
 Register 572 (MAC Address46 High Register)   

The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address46 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address46 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address46_low 0x8F4 32 RW 0xFFFFFFFF 
 Register 573 (MAC Address46 Low Register)   

The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC address of the station.
gmacgrp_mac_address47_high 0x8F8 32 RW 0xFFFF 
 Register 574 (MAC Address47 High Register)   

The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address47 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address47 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address47_low 0x8FC 32 RW 0xFFFFFFFF 
 Register 575 (MAC Address47 Low Register)   

The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC address of the station.
gmacgrp_mac_address48_high 0x900 32 RW 0xFFFF 
 Register 576 (MAC Address48 High Register)   

The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address48 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address48 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address48_low 0x904 32 RW 0xFFFFFFFF 
 Register 577 (MAC Address48 Low Register)   

The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC address of the station.
gmacgrp_mac_address49_high 0x908 32 RW 0xFFFF 
 Register 578 (MAC Address49 High Register)   

The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address49 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address49 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address49_low 0x90C 32 RW 0xFFFFFFFF 
 Register 579 (MAC Address49 Low Register)   

The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC address of the station.
gmacgrp_mac_address50_high 0x910 32 RW 0xFFFF 
 Register 580 (MAC Address50 High Register)   

The MAC Address50 High register holds the upper 16 bits of the 51st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address50 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address50 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address50_low 0x914 32 RW 0xFFFFFFFF 
 Register 581 (MAC Address50 Low Register)   

The MAC Address50 Low register holds the lower 32 bits of the 51st 6-byte MAC address of the station.
gmacgrp_mac_address51_high 0x918 32 RW 0xFFFF 
 Register 582 (MAC Address51 High Register)   

The MAC Address51 High register holds the upper 16 bits of the 52nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address51 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address51 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address51_low 0x91C 32 RW 0xFFFFFFFF 
 Register 583 (MAC Address51 Low Register)   

The MAC Address51 Low register holds the lower 32 bits of the 52nd 6-byte MAC address of the station.
gmacgrp_mac_address52_high 0x920 32 RW 0xFFFF 
 Register 584 (MAC Address52 High Register)   

The MAC Address52 High register holds the upper 16 bits of the 53rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address52 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address52 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address52_low 0x924 32 RW 0xFFFFFFFF 
 Register 585 (MAC Address52 Low Register) 

The MAC Address52 Low register holds the lower 32 bits of the 53rd 6-byte MAC address of the station.
gmacgrp_mac_address53_high 0x928 32 RW 0xFFFF 
 Register 586 (MAC Address53 High Register) 

The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address53 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address53 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address53_low 0x92C 32 RW 0xFFFFFFFF 
 Register 587 (MAC Address53 Low Register)  

The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC address of the station.
gmacgrp_mac_address54_high 0x930 32 RW 0xFFFF 
 Register 588 (MAC Address54 High Register)  

The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address54 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address54 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address54_low 0x934 32 RW 0xFFFFFFFF 
 Register 589 (MAC Address54 Low Register)  

The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC address of the station.
gmacgrp_mac_address55_high 0x938 32 RW 0xFFFF 
 Register 590 (MAC Address55 High Register)   

The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address55 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address55 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address55_low 0x93C 32 RW 0xFFFFFFFF 
 Register 591 (MAC Address55 Low Register)   

The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC address of the station.
gmacgrp_mac_address56_high 0x940 32 RW 0xFFFF 
 Register 592 (MAC Address56 High Register)   

The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address56 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address56 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address56_low 0x944 32 RW 0xFFFFFFFF 
 Register 593 (MAC Address56 Low Register)   

The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC address of the station.
gmacgrp_mac_address57_high 0x948 32 RW 0xFFFF 
 Register 594 (MAC Address57 High Register)   

The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address57 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address57 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address57_low 0x94C 32 RW 0xFFFFFFFF 
 Register 595 (MAC Address57 Low Register)  

The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC address of the station.
gmacgrp_mac_address58_high 0x950 32 RW 0xFFFF 
 Register 596 (MAC Address58 High Register)  

The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address58 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address58 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address58_low 0x954 32 RW 0xFFFFFFFF 
 Register 597 (MAC Address58 Low Register)  

The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC address of the station.
gmacgrp_mac_address59_high 0x958 32 RW 0xFFFF 
 Register 598 (MAC Address59 High Register)   

The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address59 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address59 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address59_low 0x95C 32 RW 0xFFFFFFFF 
 Register 599 (MAC Address59 Low Register)   

The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC address of the station.
gmacgrp_mac_address60_high 0x960 32 RW 0xFFFF 
 Register 600 (MAC Address60 High Register)   

The MAC Address60 High register holds the upper 16 bits of the 61st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address60 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address60 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address60_low 0x964 32 RW 0xFFFFFFFF 
 Register 601 (MAC Address60 Low Register)   

The MAC Address60 Low register holds the lower 32 bits of the 61st 6-byte MAC address of the station.
gmacgrp_mac_address61_high 0x968 32 RW 0xFFFF 
 Register 602 (MAC Address61 High Register)   

The MAC Address61 High register holds the upper 16 bits of the 62nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address61 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address61 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address61_low 0x96C 32 RW 0xFFFFFFFF 
 Register 603 (MAC Address61 Low Register)  

The MAC Address61 Low register holds the lower 32 bits of the 62nd 6-byte MAC address of the station.
gmacgrp_mac_address62_high 0x970 32 RW 0xFFFF 
 Register 604 (MAC Address62 High Register)  

The MAC Address62 High register holds the upper 16 bits of the 63rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address62 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address62 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address62_low 0x974 32 RW 0xFFFFFFFF 
 Register 605 (MAC Address62 Low Register)  

The MAC Address62 Low register holds the lower 32 bits of the 63rd 6-byte MAC address of the station.
gmacgrp_mac_address63_high 0x978 32 RW 0xFFFF 
 Register 606 (MAC Address63 High Register)   

The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address63 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address63 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address63_low 0x97C 32 RW 0xFFFFFFFF 
 Register 607 (MAC Address63 Low Register)   

The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC address of the station.
gmacgrp_mac_address64_high 0x980 32 RW 0xFFFF 
 Register 608 (MAC Address64 High Register)   

The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address64 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address64 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address64_low 0x984 32 RW 0xFFFFFFFF 
 Register 609 (MAC Address64 Low Register)  

The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC address of the station.
gmacgrp_mac_address65_high 0x988 32 RW 0xFFFF 
 Register 610 (MAC Address65 High Register)   

The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address65 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address65 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address65_low 0x98C 32 RW 0xFFFFFFFF 
 Register 611 (MAC Address65 Low Register)  

The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC address of the station.
gmacgrp_mac_address66_high 0x990 32 RW 0xFFFF 
 Register 612 (MAC Address66 High Register)  

The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address66 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address66 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address66_low 0x994 32 RW 0xFFFFFFFF 
 Register 613 (MAC Address66 Low Register)  

The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC address of the station.
gmacgrp_mac_address67_high 0x998 32 RW 0xFFFF 
 Register 614 (MAC Address67 High Register)  

The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address67 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address67 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address67_low 0x99C 32 RW 0xFFFFFFFF 
 Register 615 (MAC Address67 Low Register)  

The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC address of the station.
gmacgrp_mac_address68_high 0x9A0 32 RW 0xFFFF 
 Register 616 (MAC Address68 High Register)  

The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address68 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address68 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address68_low 0x9A4 32 RW 0xFFFFFFFF 
 Register 617 (MAC Address68 Low Register)  

The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC address of the station.
gmacgrp_mac_address69_high 0x9A8 32 RW 0xFFFF 
 Register 618 (MAC Address69 High Register)   

The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address69 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address70 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address69_low 0x9AC 32 RW 0xFFFFFFFF 
 Register 619 (MAC Address69 Low Register)   

The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC address of the station.
gmacgrp_mac_address70_high 0x9B0 32 RW 0xFFFF 
 Register 620 (MAC Address70 High Register)   

The MAC Address70 High register holds the upper 16 bits of the 71st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address70 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address70 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address70_low 0x9B4 32 RW 0xFFFFFFFF 
 Register 621 (MAC Address70 Low Register)   

The MAC Address70 Low register holds the lower 32 bits of the 71st 6-byte MAC address of the station.
gmacgrp_mac_address71_high 0x9B8 32 RW 0xFFFF 
 Register 622 (MAC Address71 High Register)   

The MAC Address71 High register holds the upper 16 bits of the 72nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address71 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address71 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address71_low 0x9BC 32 RW 0xFFFFFFFF 
 Register 623 (MAC Address71 Low Register)  

The MAC Address71 Low register holds the lower 32 bits of the 72nd 6-byte MAC address of the station.
gmacgrp_mac_address72_high 0x9C0 32 RW 0xFFFF 
 Register 624 (MAC Address72 High Register)  

The MAC Address72 High register holds the upper 16 bits of the 73rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address72 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address72 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address72_low 0x9C4 32 RW 0xFFFFFFFF 
 Register 625 (MAC Address72 Low Register)  

The MAC Address72 Low register holds the lower 32 bits of the 73rd 6-byte MAC address of the station.
gmacgrp_mac_address73_high 0x9C8 32 RW 0xFFFF 
 Register 626 (MAC Address73 High Register)  

The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address73 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address73 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address73_low 0x9CC 32 RW 0xFFFFFFFF 
 Register 627 (MAC Address73 Low Register)  

The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC address of the station.
gmacgrp_mac_address74_high 0x9D0 32 RW 0xFFFF 
 Register 628 (MAC Address74 High Register)  

The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address74 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address74 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address74_low 0x9D4 32 RW 0xFFFFFFFF 
 Register 629 (MAC Address74 Low Register) 

The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC address of the station.
gmacgrp_mac_address75_high 0x9D8 32 RW 0xFFFF 
 Register 630 (MAC Address75 High Register)   

The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address75 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address75 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address75_low 0x9DC 32 RW 0xFFFFFFFF 
 Register 631 (MAC Address75 Low Register)   

The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC address of the station.
gmacgrp_mac_address76_high 0x9E0 32 RW 0xFFFF 
 Register 632 (MAC Address76 High Register)   

The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address76 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address76 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address76_low 0x9E4 32 RW 0xFFFFFFFF 
 Register 633 (MAC Address76 Low Register)   

The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC address of the station.
gmacgrp_mac_address77_high 0x9E8 32 RW 0xFFFF 
 Register 634 (MAC Address77 High Register)   

The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address77 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address77 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address77_low 0x9EC 32 RW 0xFFFFFFFF 
 Register 635 (MAC Address77 Low Register)  

The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC address of the station.
gmacgrp_mac_address78_high 0x9F0 32 RW 0xFFFF 
 Register 636 (MAC Address78 High Register)  

The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address78 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address78 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address78_low 0x9F4 32 RW 0xFFFFFFFF 
 Register 637 (MAC Address78 Low Register)  

The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC address of the station.
gmacgrp_mac_address79_high 0x9F8 32 RW 0xFFFF 
 Register 638 (MAC Address79 High Register)  

The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address79 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address79 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address79_low 0x9FC 32 RW 0xFFFFFFFF 
 Register 639 (MAC Address79 Low Register)  

The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC address of the station.
gmacgrp_mac_address80_high 0xA00 32 RW 0xFFFF 
 Register 640 (MAC Address80 High Register)  

The MAC Address80 High register holds the upper 16 bits of the 81st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address80 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address80 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address80_low 0xA04 32 RW 0xFFFFFFFF 
 Register 641 (MAC Address80 Low Register)  
  

The MAC Address80 Low register holds the lower 32 bits of the 81st 6-byte MAC address of the station.
gmacgrp_mac_address81_high 0xA08 32 RW 0xFFFF 
 Register 642 (MAC Address81 High Register)   

The MAC Address81 High register holds the upper 16 bits of the 82nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address81 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address81 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address81_low 0xA0C 32 RW 0xFFFFFFFF 
 Register 643 (MAC Address81 Low Register)   

The MAC Address81 Low register holds the lower 32 bits of the 82nd 6-byte MAC address of the station.
gmacgrp_mac_address82_high 0xA10 32 RW 0xFFFF 
 Register 644 (MAC Address82 High Register)   

The MAC Address82 High register holds the upper 16 bits of the 83rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address82 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address82 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address82_low 0xA14 32 RW 0xFFFFFFFF 
 Register 645 (MAC Address82 Low Register)   

The MAC Address82 Low register holds the lower 32 bits of the 83rd 6-byte MAC address of the station.
gmacgrp_mac_address83_high 0xA18 32 RW 0xFFFF 
 Register 646 (MAC Address83 High Register)   

The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address83 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address83 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address83_low 0xA1C 32 RW 0xFFFFFFFF 
 Register 647 (MAC Address83 Low Register)  

The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC address of the station.
gmacgrp_mac_address84_high 0xA20 32 RW 0xFFFF 
 Register 648 (MAC Address84 High Register)  

The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address84 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address84 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address84_low 0xA24 32 RW 0xFFFFFFFF 
 Register 649 (MAC Address84 Low Register)  

The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC address of the station.
gmacgrp_mac_address85_high 0xA28 32 RW 0xFFFF 
 Register 650 (MAC Address85 High Register)  

The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address85 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address85 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address85_low 0xA2C 32 RW 0xFFFFFFFF 
 Register 651 (MAC Address85 Low Register)  

The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC address of the station.
gmacgrp_mac_address86_high 0xA30 32 RW 0xFFFF 
 Register 652 (MAC Address86 High Register)  

The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address86 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address86 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address86_low 0xA34 32 RW 0xFFFFFFFF 
 Register 653 (MAC Address86 Low Register)
  

The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC address of the station.
gmacgrp_mac_address87_high 0xA38 32 RW 0xFFFF 
 Register 654 (MAC Address87 High Register)
  

The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address87 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address87 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address87_low 0xA3C 32 RW 0xFFFFFFFF 
 Register 655 (MAC Address87 Low Register)
  

The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC address of the station.
gmacgrp_mac_address88_high 0xA40 32 RW 0xFFFF 
 Register 656 (MAC Address88 High Register)
  

The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address88 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address88 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address88_low 0xA44 32 RW 0xFFFFFFFF 
 Register 657 (MAC Address88 Low Register)
  

The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC address of the station.
gmacgrp_mac_address89_high 0xA48 32 RW 0xFFFF 
 Register 658 (MAC Address89 High Register)
  

The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address89 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address89 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address89_low 0xA4C 32 RW 0xFFFFFFFF 
 Register 659 (MAC Address89 Low Register)
  

The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC address of the station.
gmacgrp_mac_address90_high 0xA50 32 RW 0xFFFF 
 Register 660 (MAC Address90 High Register)
  

The MAC Address90 High register holds the upper 16 bits of the 91st 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address90 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address90 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address90_low 0xA54 32 RW 0xFFFFFFFF 
 Register 661 (MAC Address90 Low Register)
  

The MAC Address90 Low register holds the lower 32 bits of the 91st 6-byte MAC address of the station.
gmacgrp_mac_address91_high 0xA58 32 RW 0xFFFF 
 Register 662 (MAC Address91 High Register)
  

The MAC Address91 High register holds the upper 16 bits of the 92nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address32 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address91 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address91_low 0xA5C 32 RW 0xFFFFFFFF 
 Register 663 (MAC Address91 Low Register)
  

The MAC Address91 Low register holds the lower 32 bits of the 92nd 6-byte MAC address of the station.
gmacgrp_mac_address92_high 0xA60 32 RW 0xFFFF 
 Register 664 (MAC Address92 High Register)
  

The MAC Address92 High register holds the upper 16 bits of the 93rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address92 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address92 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address92_low 0xA64 32 RW 0xFFFFFFFF 
 Register 665 (MAC Address92 Low Register)
  

The MAC Address92 Low register holds the lower 32 bits of the 93rd 6-byte MAC address of the station.
gmacgrp_mac_address93_high 0xA68 32 RW 0xFFFF 
 Register 666 (MAC Address93 High Register)
  

The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address93 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address93 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address93_low 0xA6C 32 RW 0xFFFFFFFF 
 Register 667 (MAC Address93 Low Register)
  

The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC address of the station.
gmacgrp_mac_address94_high 0xA70 32 RW 0xFFFF 
 Register 668 (MAC Address94 High Register)
  

The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address94 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address94 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address94_low 0xA74 32 RW 0xFFFFFFFF 
 Register 669 (MAC Address94 Low Register)
  

The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC address of the station.
gmacgrp_mac_address95_high 0xA78 32 RW 0xFFFF 
 Register 670 (MAC Address95 High Register)
  

The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address95 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address95 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address95_low 0xA7C 32 RW 0xFFFFFFFF 
 Register 671 (MAC Address95 Low Register)
  

The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC address of the station.
gmacgrp_mac_address96_high 0xA80 32 RW 0xFFFF 
 Register 672 (MAC Address96 High Register)
  

The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address96 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address96 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address96_low 0xA84 32 RW 0xFFFFFFFF 
 Register 673 (MAC Address96 Low Register)
  

The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC address of the station.
gmacgrp_mac_address97_high 0xA88 32 RW 0xFFFF 
 Register 674 (MAC Address97 High Register)
  

The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address97 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address97 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address97_low 0xA8C 32 RW 0xFFFFFFFF 
 Register 675 (MAC Address97 Low Register)
  

The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC address of the station.
gmacgrp_mac_address98_high 0xA90 32 RW 0xFFFF 
 Register 676 (MAC Address98 High Register)
  

The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address99 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address99 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address98_low 0xA94 32 RW 0xFFFFFFFF 
 Register 677 (MAC Address98 Low Register)
  

The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC address of the station.
gmacgrp_mac_address99_high 0xA98 32 RW 0xFFFF 
 Register 678 (MAC Address99 High Register)

The MAC Address99 High register holds the upper 16 bits of the 6-byte 100th MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address99 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address99 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address99_low 0xA9C 32 RW 0xFFFFFFFF 
 Register 679 (MAC Address99 Low Register)
  

The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC address of the station.
gmacgrp_mac_address100_high 0xAA0 32 RW 0xFFFF 
 Register 680 (MAC Address100 High Register)
  

The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address100 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address100 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address100_low 0xAA4 32 RW 0xFFFFFFFF 
 Register 681 (MAC Address100 Low Register)
  

The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC address of the station.
gmacgrp_mac_address101_high 0xAA8 32 RW 0xFFFF 
 Register 682 (MAC Address101 High Register)
  

The MAC Address101 High register holds the upper 16 bits of the 102nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address101 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address101 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address101_low 0xAAC 32 RW 0xFFFFFFFF 
 Register 683 (MAC Address101 Low Register)
  

The MAC Address101 Low register holds the lower 32 bits of the 102nd 6-byte MAC address of the station.
gmacgrp_mac_address102_high 0xAB0 32 RW 0xFFFF 
 Register 684 (MAC Address102 High Register)
  

The MAC Address102 High register holds the upper 16 bits of the 6-byte 103rd MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address102 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address102 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address102_low 0xAB4 32 RW 0xFFFFFFFF 
 Register 685 (MAC Address102 Low Register)
  

The MAC Address102 Low register holds the lower 32 bits of the 103rd 6-byte MAC address of the station.
gmacgrp_mac_address103_high 0xAB8 32 RW 0xFFFF 
 Register 686 (MAC Address103 High Register)
  

The MAC Address103 High register holds the upper 16 bits of the 6-byte 104th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address103 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address103 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address103_low 0xABC 32 RW 0xFFFFFFFF 
 Register 687 (MAC Address103 Low Register)
  

The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC address of the station.
gmacgrp_mac_address104_high 0xAC0 32 RW 0xFFFF 
 Register 688 (MAC Address104 High Register)
  

The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address104 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address104 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address104_low 0xAC4 32 RW 0xFFFFFFFF 
 Register 689 (MAC Address104 Low Register)
  

The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC address of the station.
gmacgrp_mac_address105_high 0xAC8 32 RW 0xFFFF 
 Register 690 (MAC Address105 High Register)
  

The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address105 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address105 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address105_low 0xACC 32 RW 0xFFFFFFFF 
 Register 691 (MAC Address105 Low Register)
  

The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC address of the station.
gmacgrp_mac_address106_high 0xAD0 32 RW 0xFFFF 
 Register 692 (MAC Address106 High Register)
  

The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address106 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address106 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address106_low 0xAD4 32 RW 0xFFFFFFFF 
 Register 693 (MAC Address106 Low Register)
  

The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC address of the station.
gmacgrp_mac_address107_high 0xAD8 32 RW 0xFFFF 
 Register 694 (MAC Address107 High Register)
  

The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address107 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address107 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address107_low 0xADC 32 RW 0xFFFFFFFF 
 Register 695 (MAC Address107 Low Register)
  

The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC address of the station.
gmacgrp_mac_address108_high 0xAE0 32 RW 0xFFFF 
 Register 696 (MAC Address108 High Register)
  

The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address108 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address108 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address108_low 0xAE4 32 RW 0xFFFFFFFF 
 Register 697 (MAC Address108 Low Register)
  

The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC address of the station.
gmacgrp_mac_address109_high 0xAE8 32 RW 0xFFFF 
 Register 698 (MAC Address109 High Register)
  

The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address109 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address109 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address109_low 0xAEC 32 RW 0xFFFFFFFF 
 Register 699 (MAC Address109 Low Register)
  

The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC address of the station.
gmacgrp_mac_address110_high 0xAF0 32 RW 0xFFFF 
 Register XXX (MAC AddressXX High Register)
  

The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address110 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address110 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address110_low 0xAF4 32 RW 0xFFFFFFFF 
 Register 700 (MAC Address110 Low Register)
  

The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC address of the station.
gmacgrp_mac_address111_high 0xAF8 32 RW 0xFFFF 
 Register 701 (MAC Address111 High Register)
  

The MAC Address111 High register holds the upper 16 bits of the 6-byte 112th MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address111 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address111 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address111_low 0xAFC 32 RW 0xFFFFFFFF 
 Register 702 (MAC Address111 Low Register)
  

The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC address of the station.
gmacgrp_mac_address112_high 0xB00 32 RW 0xFFFF 
 Register 703 (MAC Address112 High Register)
  

The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address112 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address112 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address112_low 0xB04 32 RW 0xFFFFFFFF 
 Register 704 (MAC Address112 Low Register)
  

The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC address of the station.
gmacgrp_mac_address113_high 0xB08 32 RW 0xFFFF 
 Register 705 (MAC Address113 High Register)
  

The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address113 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address113 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address113_low 0xB0C 32 RW 0xFFFFFFFF 
 Register 706 (MAC Address113 Low Register)
  

The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC address of the station.
gmacgrp_mac_address114_high 0xB10 32 RW 0xFFFF 
 Register 707 (MAC Address114 High Register)
  

The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address114 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address114 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address114_low 0xB14 32 RW 0xFFFFFFFF 
 Register 708 (MAC Address114 Low Register)
  

The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC address of the station.
gmacgrp_mac_address115_high 0xB18 32 RW 0xFFFF 
 Register 709 (MAC Address115 High Register)
  

The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address115 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address115 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address115_low 0xB1C 32 RW 0xFFFFFFFF 
 Register 710 (MAC Address115 Low Register)
  

The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC address of the station.
gmacgrp_mac_address116_high 0xB20 32 RW 0xFFFF 
 Register 711 (MAC Address116 High Register)
  

The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address116 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address116 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address116_low 0xB24 32 RW 0xFFFFFFFF 
 Register 712 (MAC Address116 Low Register)
  

The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC address of the station.
gmacgrp_mac_address117_high 0xB28 32 RW 0xFFFF 
 Register 713 (MAC Address117 High Register)
  

The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode of the MAC Address117 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address117 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address117_low 0xB2C 32 RW 0xFFFFFFFF 
 Register 714 (MAC Address117 Low Register)
  

The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC address of the station.
gmacgrp_mac_address118_high 0xB30 32 RW 0xFFFF 
 Register 715 (MAC Address118 High Register)
  

The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address118 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address118 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address118_low 0xB34 32 RW 0xFFFFFFFF 
 Register 716 (MAC Address118 Low Register)
  

The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC address of the station.
gmacgrp_mac_address119_high 0xB38 32 RW 0xFFFF 
 Register 717 (MAC Address119 High Register)
  

The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address119 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address119 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address119_low 0xB3C 32 RW 0xFFFFFFFF 
 Register 718 (MAC Address119 Low Register)
  

The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC address of the station.
gmacgrp_mac_address120_high 0xB40 32 RW 0xFFFF 
 Register 719 (MAC Address120 High Register)
  

The MAC Address120 High register holds the upper 16 bits of the 6-byte 121st MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address120 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address120 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address120_low 0xB44 32 RW 0xFFFFFFFF 
 Register 720 (MAC Address120 Low Register)
  

The MAC Address120 Low register holds the lower 32 bits of the 121st 6-byte MAC address of the station.
gmacgrp_mac_address121_high 0xB48 32 RW 0xFFFF 
 Register 721 (MAC Address121 High Register)
  

The MAC Address121 High register holds the upper 16 bits of the 122nd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address121 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address121 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address121_low 0xB4C 32 RW 0xFFFFFFFF 
 Register 722 (MAC Address121 Low Register)
  

The MAC Address121 Low register holds the lower 32 bits of the 122nd 6-byte MAC address of the station.
gmacgrp_mac_address122_high 0xB50 32 RW 0xFFFF 
 Register 723 (MAC Address122 High Register)
  

The MAC Address122 High register holds the upper 16 bits of the 123rd 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address122 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address122 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address122_low 0xB54 32 RW 0xFFFFFFFF 
 Register 724 (MAC Address122 Low Register)
  

The MAC Address122 Low register holds the lower 32 bits of the 123rd 6-byte MAC address of the station.
gmacgrp_mac_address123_high 0xB58 32 RW 0xFFFF 
 Register 725 (MAC Address123 High Register)
  

The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address123 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address123 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address123_low 0xB5C 32 RW 0xFFFFFFFF 
 Register 726 (MAC AddressXX 123 Register)
  

The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC address of the station.
gmacgrp_mac_address124_high 0xB60 32 RW 0xFFFF 
 Register 727 (MAC Address124 High Register)
  

The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address124 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address124 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address124_low 0xB64 32 RW 0xFFFFFFFF 
 Register 728 (MAC Address124 Low Register)
  

The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC address of the station.
gmacgrp_mac_address125_high 0xB68 32 RW 0xFFFF 
 Register 729 (MAC Address125 High Register)
  

The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address125 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address125 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address125_low 0xB6C 32 RW 0xFFFFFFFF 
 Register 730 (MAC Address125 Low Register)
  

The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC address of the station.
gmacgrp_mac_address126_high 0xB70 32 RW 0xFFFF 
 Register 731 (MAC Address126 High Register)
  

The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address126 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address126 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address126_low 0xB74 32 RW 0xFFFFFFFF 
 Register 732 (MAC Address126 Low Register)
  

The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC address of the station.
gmacgrp_mac_address127_high 0xB78 32 RW 0xFFFF 
 Register 733 (MAC Address127 High Register)
  

The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC address of the station.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) of the MAC Address127 Low Register are written. For proper synchronization updates, consecutive writes to this MAC Address127 Low Register must be performed after at least four clock cycles in the destination clock domain.
gmacgrp_mac_address127_low 0xB7C 32 RW 0xFFFFFFFF 
 Register 734 (MAC Address127 Low Register)
  

The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC address of the station.
dmagrp_bus_mode 0x1000 32 RW 0x20101 
 Register 0 (Bus Mode Register) 

The Bus Mode register establishes the bus operating modes for the DMA.
dmagrp_transmit_poll_demand 0x1004 32 RW 0x0 
 Register 1 (Transmit Poll Demand Register) 

The Transmit Poll Demand register enables the Tx DMA to check whether or not the DMA owns the current descriptor. The Transmit Poll Demand command is given to wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the Suspend mode because of an Underflow error in a transmitted frame or the unavailability of descriptors owned by it. You can give this command anytime and the Tx DMA resets this command when it again starts fetching the current descriptor from host memory. When this register is read, it always returns zero.
dmagrp_receive_poll_demand 0x1008 32 RW 0x0 
Register 2 (Receive Poll Demand Register) 

The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is used to wake up the Rx DMA from the SUSPEND state. The RxDMA can go into the SUSPEND state only because of the unavailability of descriptors it owns. When this register is read, it always returns zero.
dmagrp_receive_descriptor_list_address 0x100C 32 RW 0x0 
Register 3 (Receive Descriptor List Address Register) 

The Receive Descriptor List Address register points to the start of the Receive Descriptor List. The descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given.

You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can be written with a new descriptor list address. When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.

If this register is not changed when the SR bit is set to 0, then the DMA takes the descriptor address where it was stopped earlier.
dmagrp_transmit_descriptor_list_address 0x1010 32 RW 0x0 
Register 4 (Transmit Descriptor List Address Register)

The Transmit Descriptor List Address register points to the start of the Transmit Descriptor List. The descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low. 

You can write to this register only when the Tx DMA has stopped, that is, Bit 13 (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly programmed descriptor base address.

If this register is not changed when the ST bit is set to 0, then the DMA takes the descriptor address where it was stopped earlier.
dmagrp_status 0x1014 32 RW 0x0 
Register 5 (Status Register)  

The Status register contains all status bits that the DMA reports to the host. The Software driver reads this register during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The bits of this register are not cleared when read. Writing 1'b1 to (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit in Register 7 (Interrupt Enable Register).
dmagrp_operation_mode 0x1018 32 RW 0x0 
 Register 6 (Operation Mode Register) 

The Operation Mode register establishes the Transmit and Receive operating modes and commands. This register should be the last CSR to be written as part of the DMA initialization. This register is also present in the GMAC-MTL configuration with unused and reserved bits 24, 13, 2, and 1.
dmagrp_interrupt_enable 0x101C 32 RW 0x0 
 Register 7 (Interrupt Enable Register) 

The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
dmagrp_missed_frame_and_buffer_overflow_counter 0x1020 32 RO 0x0 
Register 8 (Missed Frame and Buffer Overflow Counter Register) 

The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate missed frames because of the host buffer being unavailable. Bits[27:17] indicate missed frames because of buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL.
dmagrp_receive_interrupt_watchdog_timer 0x1024 32 RW 0x0 
 Register 9 (Receive Interrupt Watchdog Timer Register) 

This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt (Bit 6) of Register 5 (Status Register)
dmagrp_axi_bus_mode 0x1028 32 RW 0x110001 
Register 10 (AXI Bus Mode Register)
dmagrp_ahb_or_axi_status 0x102C 32 RO 0x0 
 Register 11 (AHB or AXI Status Register) 

This register provides the active status of the AHB master interface or AXI interface's read and write channels. This register is present and valid only in the GMAC-AHB and GMAC-AXI configurations. This register is useful for debugging purposes. In addition, this register is valid only in the Channel 0 DMA when multiple channels are present in the AV mode.
dmagrp_current_host_transmit_descriptor 0x1048 32 RO 0x0 
 Register 18 (Current Host Transmit Descriptor Register) 

The Current Host Transmit Descriptor register points to the start address of the current Transmit Descriptor read by the DMA.
dmagrp_current_host_receive_descriptor 0x104C 32 RO 0x0 
 Register 19 (Current Host Receive Descriptor Register) 

The Current Host Receive Descriptor register points to the start address of the current Receive Descriptor read by the DMA.
dmagrp_current_host_transmit_buffer_address 0x1050 32 RO 0x0 
 Register 20 (Current Host Transmit Buffer Address Register) 

The Current Host Transmit Buffer Address register points to the current Transmit Buffer Address being read by the DMA.
dmagrp_current_host_receive_buffer_address 0x1054 32 RO 0x0 
 Register 21 (Current Host Receive Buffer Address Register) 

The Current Host Receive Buffer Address register points to the current Receive Buffer address being read by the DMA.
dmagrp_hw_feature 0x1058 32 RO 0xF0D69BF 
 Register 22 (HW Feature Register) 

This register indicates the presence of the optional features or functions of the DWC_gmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Note: All bits are set or reset as per the selection of features during the DWC_gmac configuration.